公开(公告)号：US20210375672A1

公开(公告)日：2021-12-02

申请号：US17112119

申请日：2020-12-04

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Hao Chun Liu ,  Po-Hao Tsai ,  Chih-Hsien Lin ,  Ching-Wen Hsiao

IPC分类号： H01L21/768 ,  H01L21/48 ,  H01L23/532 ,  H01L23/00

摘要： A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

公开(公告)号：US20160190127A1

公开(公告)日：2016-06-30

申请号：US15063310

申请日：2016-03-07

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Jun-De Jin ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/812 ,  H01L29/78 ,  H01L21/8236 ,  H01L29/66

CPC分类号： H01L27/0883 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/812 ,  H03F1/223 ,  H03F3/213

摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell.

摘要翻译： 为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P基板中的N阱中的肖特基MOSFET，源极之间具有水平或垂直通道 ，漏极和栅电极。 增强型MOSFET的源节点和肖特基MOSFET的源极节点连接在一起形成功率单元。

公开(公告)号：US20220238697A1

公开(公告)日：2022-07-28

申请号：US17333592

申请日：2021-05-28

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Szu-Ying Chen

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L29/417

摘要： A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

公开(公告)号：US08848467B1

公开(公告)日：2014-09-30

申请号：US13873526

申请日：2013-04-30

申请人： Taiwan Semiconductor Manfacturing Co. Ltd.

发明人： Chung-Hsien Hua ,  Yu-Hao Hsu ,  Chen-Li Yang ,  Cheng Hung Lee

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1078 ,  G11C7/1096 ,  G11C8/08 ,  G11C11/419 ,  G11C11/5628

摘要： An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.

摘要翻译： 公开了一种集成驱动器系统。 驱动器系统包括解码逻辑和驱动器部分。 解码逻辑被配置为接收选择信号和数据信号。 驱动器部分被配置为根据解码的信号产生驱动器信号。

公开(公告)号：US20240213330A1

公开(公告)日：2024-06-27

申请号：US18433872

申请日：2024-02-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee

IPC分类号： H01L29/165 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/165 ,  C30B25/10 ,  C30B25/12 ,  C30B25/165 ,  H01L21/02315 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/3247 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795

摘要： Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

公开(公告)号：US20140231872A1

公开(公告)日：2014-08-21

申请号：US13771249

申请日：2013-02-20

申请人： TAIWAN SEMICONDUCTOR MANFACTURING CO., LTD.

发明人： Jean-Pierre Colinge ,  Kuo-Cheng Ching

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7843 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

摘要翻译： 翅片内部的膨胀材料（通常为散热片半导体的氧化物）的FinFET导致在FinFET通道内显着增加电荷载流子迁移率的应变。 该概念可以应用于p型或n型FinFET。 对于p型FinFET，膨胀材料位于源极和漏极区域的下方。 对于n型FinFET，膨胀的材料位于通道区域的下方。 溶胀材料可以在源极和漏极区域具有或不具有应变诱导外延使用，并且可以提供比单独应变诱导外延可实现的更大的应变。

公开(公告)号：US20230131688A1

公开(公告)日：2023-04-27

申请号：US17832979

申请日：2022-06-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Da-Yuan Lee ,  Weng Chang

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306

摘要： Embodiments include a nanoFET device and method for forming the same, the nanoFET having channel regions which have been thinned during a gate replacement process to remove etching residue. In some embodiments, the channel regions become dog bone shaped. In some embodiments, the ends of the channel regions have vertical protrusions or horns resulting from a previous trimming process which is performed prior to depositing sidewall spacers.

公开(公告)号：US20220367610A1

公开(公告)日：2022-11-17

申请号：US17875026

申请日：2022-07-27

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Chen-Yin HSU ,  Chun Li WU ,  Ching-Hung KAO

IPC分类号： H01L49/02

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.

公开(公告)号：US20220302105A1

公开(公告)日：2022-09-22

申请号：US17836899

申请日：2022-06-09

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ming-Fu Tsai ,  Tzu-Heng Chang ,  Yu-Ti Su ,  Kai-Ping Huang

IPC分类号： H01L27/02

摘要： An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

公开(公告)号：US20160043576A1

公开(公告)日：2016-02-11

申请号：US14918615

申请日：2015-10-21

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Jun-De JIN ,  Fan-Ming KUO ,  Huan-Neng CHEN ,  Ming-Hsien TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH

IPC分类号： H02J5/00 ,  H02J17/00

CPC分类号： H02J5/005 ,  H01F5/00 ,  H01F17/0006 ,  H01F38/14 ,  H01F2017/0086 ,  H02J17/00 ,  H02J50/12

摘要： A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.

摘要翻译： 变压器包括第一和第二半导体衬底。 第一半导体衬底包括第一电路，提供第一阻抗的第一线圈和与第一线圈并联耦合的第一电容器。 第二半导体衬底包括第二电路，提供第二阻抗并与第一线圈感应耦合的第二线圈以及与第二线圈并联耦合的第二电容器。