公开(公告)号：US06731542B1

公开(公告)日：2004-05-04

申请号：US10313444

申请日：2002-12-05

申请人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

发明人： Binh Q. Le ,  Michael Achter ,  Lee Cleveland ,  Chen Pauling

IPC分类号： G11C1606

CPC分类号： G11C16/26 ,  G11C16/0491

摘要： A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

摘要翻译： 公开了一种用于在读取操作期间感测目标单元中的电流的存储器电路装置。 根据一个示例性实施例，存储器电路装置包括目标单元和与目标单元相邻的第一相邻单元。 第一目标单元具有连接到地的第一位线; 目标单元还具有连接到感测电路的第二位线。 第一相邻小区与目​​标小区共享第二位线; 在读取操作期间，第一相邻单元还具有连接到感测电路的第三位线。 存储器电路装置在目标单元的读取操作期间以快速和准确的方式导致增加的误差容限。

公开(公告)号：US06515903B1

公开(公告)日：2003-02-04

申请号：US10050254

申请日：2002-01-16

申请人： Binh Q. Le ,  Pau-Lin Chen

发明人： Binh Q. Le ,  Pau-Lin Chen

IPC分类号： G11C1604

CPC分类号： G11C16/30

摘要： A system is disclosed for generating a regulated negative charge pump voltage for flash memory operations, wherein a capacitive voltage divider circuit comprising one or more MOS capacitors is configured to respond to the regulated output voltage of a negative charge pump circuit and an output circuit source loading and generate a voltage divider output signal associated therewith. The system also includes an initialization circuit which is configured to precharge the capacitors of the MOS capacitor voltage divider with a reference voltage. The system further includes a bias circuit operable to generate a bias voltage which is used in association with the MOS capacitors to insure they operate above a bias voltage which will maintain a minimum target capacitance within the voltage divider, resulting in a stable target regulation voltage. The negative regulator also includes an output circuit operable to source the negative charge pump output voltage to a supply voltage, and a negative regulator control circuit operably coupled to the initialization circuit and the capacitive voltage divider circuit, and operable to receive the bias circuit voltage and the associated MOS capacitor voltage divider circuit output, and operable to receive a negative charge pump output voltage and regulate an output circuit source loading via the supply voltage to produce a feedback to the negative charge pump circuit based on the target voltage value established by the MOS capacitor voltage divider, thereby creating a reduced area negative regulator used in conjunction with a negative charge pump circuit, which maintains a low power and simple regulator design, to produce a regulated charge pump output which may be used as a pumped voltage for various mode operations of memory cells.

摘要翻译： 公开了一种用于产生用于闪速存储器操作的调节负电荷泵电压的系统，其中包括一个或多个MOS电容器的电容分压器电路被配置为响应负电荷泵电路的调节输出电压和输出电路源负载 并产生与其相关联的分压器输出信号。 该系统还包括初始化电路，其被配置为用参考电压对MOS电容器分压器的电容器预充电。 该系统还包括一个可以产生与MOS电容器相关联使用的偏置电压的偏置电路，以确保它们工作在偏置电压以上，该偏置电压将保持分压器内的最小目标电容，导致稳定的目标调节电压。 负调节器还包括可操作地将负电荷泵输出电压输出到电源电压的输出电路，以及可操作地耦合到初始化电路和电容分压器电路的负调节器控制电路，并且可操作以接收偏置电路电压和 相关的MOS电容器分压器电路输出，并且可操作以接收负电荷泵输出电压并且通过电源电压调节输出电路源负载，以基于由MOS建立的目标电压值向负电荷泵电路产生反馈 电容器分压器，从而形成一个与负电荷泵电路结合使用的减小面积负调节器，负电荷泵电路保持低功率和简单的调节器设计，以产生调节的电荷泵输出，其可用作各种模式操作的泵浦电压 的记忆细胞。

公开(公告)号：US06370061B1

公开(公告)日：2002-04-09

申请号：US09884583

申请日：2001-06-19

申请人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

发明人： Santosh K. Yachareni ,  Kazuhiro Kurihara ,  Binh Q. Le ,  Michael S. C. Chung

IPC分类号： G11C1634

CPC分类号： G11C16/3459 ,  G11C16/04 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

摘要翻译： 本发明涉及闪存系统和确定核心单元的阈值电压的方法。 在一个示例性系统中，提供了表征编程单元阵列的阈值电压分布的高端的方法。 根据本发明，提出了一种示例性的系统和方法，以通过高耐压周边环形晶体管和字线驱动晶体管可操作地应用变化的特征信号，该晶体管和字线驱动晶体管通过高于施加的变化的升压栅极电压而被驱动为饱和 表征信号，以提供核心单元的VT的精确确定的方式，通过比较参考单元中的导通与通过施加到核心单元的变化表征信号产生的核心单元中的导通的比较 门。

公开(公告)号：US06292406B1

公开(公告)日：2001-09-18

申请号：US09609678

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/30

摘要： Control circuitry and a method for generating an accurate boosted wordline voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Memory core transistors are provided which have their conduction path being coupled between a power supply voltage and a ground potential. Differential amplifier circuitry is responsive to a boost signal and a reference voltage for generating a select wordline voltage. The select wordline voltage is decreased when the wordline voltage is higher than a desired voltage and is increased when the wordline voltage is lower than the desired voltage. The control gates of the memory core transistors are responsive to the select wordline voltage.

摘要翻译： 提供了控制电路和用于在读操作模式期间为半导体存储器件中的所选择的存储器核心单元产生精确提升的字线电压的方法。 提供存储芯体晶体管，其导通路径耦合在电源电压和地电位之间。 差分放大器电路响应于升压信号和用于产生选择字线电压的参考电压。 当字线电压高于期望电压时，选择字线电压降低，当字线电压低于期望电压时，选择字线电压降低。 存储核心晶体管的控制栅极响应于选择字线电压。

公开(公告)号：US06255799B1

公开(公告)日：2001-07-03

申请号：US09474515

申请日：1999-12-29

申请人： Binh Q. Le ,  Ark L. Lew ,  Paul D. Schwartz ,  Albert C. Sadilek ,  Joseph J. Suter ,  Jason E. Jenkins ,  Sharon X. Ling

发明人： Binh Q. Le ,  Ark L. Lew ,  Paul D. Schwartz ,  Albert C. Sadilek ,  Joseph J. Suter ,  Jason E. Jenkins ,  Sharon X. Ling

IPC分类号： H02J700

CPC分类号： A43B7/04 ,  A43B3/00 ,  A43B3/0005 ,  A43B3/0015 ,  A43B13/203 ,  H02J7/1415 ,  H02K7/1853 ,  Y10S320/34

摘要： The invention comprises a means for generating energy while walking or running for storage in a rechargeable battery. One embodiment uses lever arm movement in the heel of a shoe resulting from normal walking or running to generate energy from a built-in generator. The linear or rotational motion of the lever arm engages the circular gear assembly and turns the generator/motor/turbine, thus generating power. The second embodiment uses fluid reservoirs embedded in the shoes. Pressure changes resulting from normal walking or running moves the fluid through a narrow channel connecting two reservoirs, thus generating power by rotating a flywheel and an attached motor/generator/turbine in the middle of the channel. Secondary (rechargeable) batteries are incorporated into the invention either in an integrated form or as an add-on design. Additional features include a digital diagnostic data output, which would serves as a “fuel gauge” for the secondary batteries, and a smart charging circuit that efficiently controls battery charging from a generator output that varies with step rate and force.

摘要翻译： 本发明包括用于在行走或运行以在可再充电电池中存储时产生能量的装置。 一个实施例使用杠杆臂运动在鞋的鞋跟中，由正常步行或跑步产生，以产生来自内置发电机的能量。 杠杆臂的线性或旋转运动与圆形齿轮组件接合并转动发电机/电动机/涡轮机，从而产生动力。 第二实施例使用嵌入鞋中的流体储存器。 由正常步行或跑步引起的压力变化使流体通过连接两个储存器的狭窄通道，从而通过在通道中间旋转飞轮和连接的电动机/发电机/涡轮来产生动力。 次级（可充电）电池以集成形式或附加设计结合到本发明中。 附加功能包括数字诊断数据输出，它将作为二次电池的“电量表”，以及一个智能充电电路，可以有效地控制发电机输出的电池充电，该发电机输出随着步进速率和力而变化。

公开(公告)号：US6157167A

公开(公告)日：2000-12-05

申请号：US69255

申请日：1998-04-29

申请人： Paul D. Schwartz ,  Binh Q. Le ,  Ark L. Lew ,  Joseph J. Suter

发明人： Paul D. Schwartz ,  Binh Q. Le ,  Ark L. Lew ,  Joseph J. Suter

IPC分类号： H02J7/00

CPC分类号： H02J7/0016 ,  H02J7/0021

摘要： A microprocessor-based charge control architecture which provides individual battery cell charge control in order to insure an equality of charge among all cells in a rechargeable battery cell array during a single charge cycle. The array is arranged in parallel strings with an identical number of cells in series in each string. The microprocessor controls the amount of charge current in each battery cell via a shunt element for each battery cell, and adjusts the shunt element to bypass a portion of the string current for each battery cell. The invention also permits charge control algorithms to be conveniently updated, provides individual cell coulometry, and autonomously monitors and corrects conditions which can result in battery failure. Any type of rechargeable battery cell and array size can be accommodated. The array size can be set to accommodate the specific voltage and load current requirements of each application.

摘要翻译： 一种基于微处理器的电荷控制架构，其提供单独的电池单元充电控制，以便在单个充电周期期间确保可再充电电池单元阵列中的所有单元之间的电荷相等。 阵列排列成与每个串中具有相同数量的单元格的并行串。 微处理器通过每个电池单元的分流元件控制每个电池单元中的充电电流量，并且调节分流元件以绕过每个电池单元的串电流的一部分。 本发明还允许方便地更新电荷控制算法，提供单个电池库仑计，并且自动监视和校正可能导致电池故障的条件。 可以容纳任何类型的可充电电池和阵列尺寸。 阵列大小可以设置为适应每个应用的具体电压和负载电流要求。

公开(公告)号：US5978266A

公开(公告)日：1999-11-02

申请号：US24880

申请日：1998-02-17

申请人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

发明人： Pau-ling Chen ,  Shane C. Hollmer ,  Binh Q. Le ,  Michael S. Chung

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.

摘要翻译： 提供了一种用于在编程期间偏置NAND阵列EEPROM以允许阵列在进入穿透之前被进一步缩小的方法。 NAND阵列的接地选择晶体管的源极被偏置为Vcc而不是接地，以减小接地选择晶体管的源极和漏极两端的电压降。 结果，在获得穿通之前，可以进一步缩短接地选择晶体管的沟道长度，从而产生更高密度的EEPROM。

公开(公告)号：US06424570B1

公开(公告)日：2002-07-23

申请号：US09892189

申请日：2001-06-26

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： H02M3/073

摘要： A system is described for generating a charge pump voltage for flash memory operations, wherein a supply voltage detection circuit (e.g., analog to digital converter, digital thermometer) is configured to detect a supply voltage value and generate one or more supply voltage level detection signals associated therewith. The system further includes a charge pump circuit comprising one or more stages operable to receive a supply voltage and generate the charge pump output voltage having a value greater than the supply voltage, and a charge pump compensation circuit operably coupled to the supply voltage detection circuit and the charge pump circuit. The charge pump compensation circuit is operable to receive the one or more output signals from the supply voltage detection circuit and modulate a capacitive loading associated with the charge pump circuit based on the one or more output signals, thereby creating an improved low power charge pump which uses a modulated pumping capacitance to compensate for fluctuations of the input power supply (for example, VCC), to produce a slow ripple and low noise output which may be used as a pumped voltage for various mode operations (e.g., erase, program modes) of memory cells.

摘要翻译： 描述了一种用于产生用于闪速存储器操作的电荷泵电压的系统，其中电源电压检测电路（例如，模数转换器，数字温度计）被配置为检测电源电压值并产生一个或多个电源电压电平检测信号 相关联。 该系统还包括电荷泵电路，其包括一个或多个级，可操作以接收电源电压并产生具有大于电源电压的值的电荷泵输出电压;以及电荷泵补偿电路，其可操作地耦合到电源电压检测电路和 电荷泵电路。 电荷泵补偿电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于该一个或多个输出信号调制与电荷泵电路相关联的电容性负载，从而产生改进的低功率电荷泵， 使用调制的泵浦电容来补偿输入电源的波动（例如VCC），以产生慢波纹和低噪声输出，其可用作用于各种模式操作（例如擦除，编程模式）的泵浦电压， 的记忆细胞。

公开(公告)号：US06292399B1

公开(公告)日：2001-09-18

申请号：US09609897

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

摘要翻译： 提供控制电路和在读操作模式期间为半导体存储器件中的选定存储核心单元产生准确的漏极电压的方法。 提供选择栅极晶体管，其导通路径耦合在所选存储核心单元之一的电源电压和漏极之间。 差分放大器电路响应于对应于所选择的存储器单元的漏极电压的位线电压和用于产生选择栅极电压的参考电压。 当位线电压高于目标电压时，选择栅极电压降低，并且当位线电压低于目标电压时，选择栅极电压增加。 源极跟随器电路响应选择栅极电压以产生保持在目标电压的位线电压。 选择栅极晶体管的控制栅极被连接以接收选择栅极电压，以将所选择的存储器核心单元的漏极处的电压保持为大致恒定。

公开(公告)号：US06208561B1

公开(公告)日：2001-03-27

申请号：US09593303

申请日：2000-06-13

申请人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/08

摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

摘要翻译： 提供了一种用于降低闪存X解码器中的电容负载以便精确地将电压控制为选择的字线和块选择线的装置和方法。 解码结构分别将第一升压电压施加到字线N阱区域，并将第二升压电压施加到所选择的字线，以便由于与字线N阱区域相关联的重电容性负载而减小所选字线上的容性负载。 解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载， 井区。 因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。