公开(公告)号：US20240296269A1

公开(公告)日：2024-09-05

申请号：US18178463

申请日：2023-03-03

Applicant: Cadence Design Systems, Inc.

Inventor： Mitchell G. Poplack ,  Bhoumik Shah ,  Jennifer Lee

IPC: G06F30/3308

CPC classification number: G06F30/3308

Abstract: The systems and methods described herein include emulators that implement wrappers comprising instrumentation logic for the emulator components (e.g., memories) to perform certain memory-related functions. These functions allow the physical binary memories of the emulator to behave as a ternary memory. The memory wrappers include instrumentation logic around logic of the physical binary memories. In some cases, embodiments generate the wrappers for the user memory, rather than performing conventional synthesis functions for user-design memories. The inputs include the user ternary RTL, as well as additional potential inputs for pre-compiler control. The wrappers instantiate the operations, such as MPRs or MPWs, and create the ternary-memory support logic to, for example, prevent unknown-value writes and to output unknown values X for unknown-value reads.

公开(公告)号：US11983538B2

公开(公告)日：2024-05-14

申请号：US17659569

申请日：2022-04-18

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Ajay A. Ingle

IPC: G06F9/38 ,  G06F12/0855

CPC classification number: G06F9/3834 ,  G06F12/0855

Abstract: Techniques are disclosed relating to a processor load-store unit. In some embodiments, the load-store unit is configured to execute load/store instructions in parallel using first and second pipelines and first and second tag memory arrays. In tag write conflict situations, the load-store unit may arbitrate between the first and second pipelines to ensure the first and second tag memory array contents remain identical. In some embodiments, a data cache tag replay scheme is utilized. In some embodiments, executing load/store instructions in parallel with fills, probes, and store-updates, using separate but identical tag memory arrays, may advantageously improve performance.

公开(公告)号：US11947887B1

公开(公告)日：2024-04-02

申请号：US17953618

申请日：2022-09-27

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Brian Foutz ,  Prateek Kumar Rai ,  Sarthak Singhal ,  Christos Papameletis ,  Vivek Chickermane

IPC: G06F30/333 ,  G06F30/327 ,  G01R31/3185

CPC classification number: G06F30/333 ,  G06F30/327 ,  G01R31/318583

Abstract: A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes the instructions. The instructions include an EDA application that includes a test-point flop allocation module that is configured to evaluate the circuit netlist to determine compatibility of the test-point nodes in the circuit netlist. The test-point flop allocation module can further allocate each of the test-point flops to a test-point sharing group comprising a plurality of compatible test-point nodes. The EDA application also includes a circuit layout module configured to generate a circuit layout associated with the circuit design, the circuit layout comprising the functional logic and scan-chains comprising the test-point flops allocated to the test-point sharing groups in response to the circuit netlist. The circuit layout is employable to fabricate an integrated circuit (IC) chip.

公开(公告)号：US11900135B1

公开(公告)日：2024-02-13

申请号：US16212363

申请日：2018-12-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G Poplack ,  Yuhei Hayashi

IPC: G06F3/00 ,  G06F9/455

CPC classification number: G06F9/45504

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

公开(公告)号：US11893336B1

公开(公告)日：2024-02-06

申请号：US17499414

申请日：2021-10-12

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC: G06F30/398 ,  G06F119/18 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F2119/12 ,  G06F2119/18

Abstract: An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.

公开(公告)号：US11876650B2

公开(公告)日：2024-01-16

申请号：US17978422

申请日：2022-11-01

Applicant: Cadence Design Systems, Inc.

Inventor： Prashant Choudhary ,  Nanyang Wang

IPC: H04L25/03

CPC classification number: H04L25/03076 ,  H04L25/03318

Abstract: An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.

公开(公告)号：US11861452B1

公开(公告)日：2024-01-02

申请号：US16443634

申请日：2019-06-17

Applicant: Cadence Design Systems, Inc.

Inventor： Ming Kai Hsu

IPC: G06N3/063 ,  G10L25/30 ,  G06F17/18 ,  G06N3/047

CPC classification number: G06N3/063 ,  G06F17/18 ,  G06N3/047 ,  G10L25/30

Abstract: Quantized softmax layers in neural networks are described. Some embodiments involve receiving, at an input to a softmax layer of a neural network from an intermediate layer of the neural network, a non-normalized output comprising a plurality of intermediate network decision values. Then for each intermediate network decision value of the plurality of intermediate network decision values, the embodiment involves: calculating a difference between the intermediate network decision value and a maximum network decision value; requesting, from a lookup table, a corresponding lookup table value using the difference between the intermediate network decision value and the maximum network decision value; and selecting the corresponding lookup table value as a corresponding decision value. A normalized output is then generated comprising the corresponding lookup table value for said each intermediate network decision value of the plurality of intermediate network decision values.

公开(公告)号：US11831153B1

公开(公告)日：2023-11-28

申请号：US16940679

申请日：2020-07-28

Applicant: Cadence Design Systems, Inc.

Inventor： Phalguni Bala ,  Manjunath Karikatti ,  Navin Kumar Mishra

IPC: H02H9/04 ,  H01L25/18 ,  H03H7/01

CPC classification number: H02H9/046 ,  H01L25/18 ,  H03H7/0115 ,  H03H2210/026

Abstract: A tuned single-coil inductor is implemented between a signal driver output and external contact of an ESD-protected integrated circuit (IC) die and more specifically between the parasitic capacitances of the signal driver and the contact-coupled ESD (electrostatic discharge) element to form a Pi (π) filter that enhances signaling bandwidth at the target signaling rate of the IC die. The signal driver may be implemented with output-stage data serialization circuitry disposed in series between source terminals of a thick-oxide drive transistor and a power rail to avoid explicit level-shifting circuitry between the relatively low core voltage domain and relatively high I/O voltage domain.

公开(公告)号：US11829276B1

公开(公告)日：2023-11-28

申请号：US17678130

申请日：2022-02-23

Applicant: Cadence Design Systems, Inc.

Inventor： Kunal Amar Chhabriya ,  Roque Alejandro Arcudia Hernandez ,  Xin Mu

IPC: G06F11/34 ,  G06F13/42 ,  G06F11/22

CPC classification number: G06F11/349 ,  G06F11/221 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Embodiments include herein are directed towards a system and method for monitoring compliance patterns. Embodiments may include a re-timer device-under-test configured to transmit a truncated compliance pattern associated with a PCIe compliance mode. Embodiments may further include a BFM monitor configured to receive the truncated compliance pattern and to identify a communication signal associated with the truncated compliance pattern. The BFM monitor may be further configured to discard at least one unexpected symbol on at least one lane associated with the communication signal and to collect compliance patterns on all lanes of the communication signal. The BFM monitor may be further configured to align one or more lane FIFOs based upon skew and to enable one or more compliance pattern checkers.

公开(公告)号：US11811362B1

公开(公告)日：2023-11-07

申请号：US17983359

申请日：2022-11-08

Applicant: Cadence Design Systems, Inc.

Inventor： Alberto Baldisserotto ,  Aida Varzaghani

IPC: H03B5/04 ,  H03L7/099 ,  H03L1/00 ,  H03L1/02

CPC classification number: H03B5/04 ,  H03L1/00 ,  H03L1/02 ,  H03L7/099

Abstract: Aspects of the present disclosure include systems and methods for temperature adaptive voltage controlled oscillators. In one example, a voltage controlled oscillator includes a cross junction circuit electrically coupled to a temperature dependent input current, and an inductor circuit electrically coupled to the cross junction circuit. The voltage controlled oscillator additionally includes a capacitor bank circuit electrically coupled to the inductor circuit, and an input node that receives a control voltage. The voltage controlled oscillator further includes an output node configured to provide an oscillation frequency output, wherein the oscillation frequency output is controlled by the control voltage.