公开(公告)号：US09070623B2

公开(公告)日：2015-06-30

申请号：US12897559

申请日：2010-10-04

Applicant: Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Kuei Shun Chen ,  Cheng Cheng Kuo ,  George Liu ,  Tsung-Chieh Tsai ,  Yuhi-Jier Mii

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7831

Abstract: Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.

Abstract translation: 公开了形成半导体结构和半导体结构的方法。 在一个实施例中，一种方法包括在衬底上形成栅极电介质层，在栅极电介质层上形成栅极电极层，并蚀刻栅极电极层和栅极电介质层以形成水平栅极结构和垂直栅极结构， 其中所述水平栅极结构和所述垂直栅极结构通过互连部分连接。 该方法还包括形成覆盖水平栅极结构和垂直栅极结构的光致抗蚀剂，其中光致抗蚀剂具有暴露水平栅极结构和垂直栅极结构之间的互连部分的间隙，然后蚀刻互连部分。

公开(公告)号：US08692351B2

公开(公告)日：2014-04-08

申请号：US12753272

申请日：2010-04-02

Applicant: Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

Inventor： Cheng Cheng Kuo ,  Luke Lo ,  Minghsing Tsai ,  Ken-Yu Chang ,  Jye-Yen Cheng ,  Jeng-Shiun Ho ,  Hua-Tai Lin ,  Chih-Hsiang Yao

IPC: H01L21/70

CPC classification number: H01L21/76838 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.

Abstract translation: 在本公开中描述了用于改善密集到隔离图案转移区域附近的处理窗口的半导体集成电路线结构和在布局处理中实现线结构的技术。 所公开的结构包括半导体衬底和衬底上方的材料层。 材料层具有紧密间隔的密集线结构，紧密密集线结构旁边的隔离线结构，以及形成在密集线附近和隔离线结构处的虚拟线肩结构。 虚拟线肩结构的一端连接到隔离线结构，另一端以基本垂直于隔离线结构的方向远离隔离线结构延伸。

公开(公告)号：US20120072874A1

公开(公告)日：2012-03-22

申请号：US12884442

申请日：2010-09-17

Applicant: Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J.H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

Inventor： Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J.H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

公开(公告)号：US08703595B2

公开(公告)日：2014-04-22

申请号：US13299152

申请日：2011-11-17

Applicant: Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

Inventor： Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

IPC: H01L21/336

CPC classification number: H01L27/0207 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823456 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成多个虚拟栅极。 虚拟门沿着第一轴延伸。 该方法包括在伪栅极上形成掩模层。 掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。 开口暴露虚拟门的第一部分并保护虚拟门的第二部分。 开口的尖端部分的宽度大于开口的非尖端部分的宽度。 使用光学邻近校正（OPC）工艺形成掩模层。 该方法包括用多个第一金属栅极替换伪栅极的第一部分。 该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

公开(公告)号：US08656319B2

公开(公告)日：2014-02-18

申请号：US13368919

申请日：2012-02-08

Applicant: Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

Inventor： Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Tzu-Chun Lo ,  Chih-Wei Hsu ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Wen-Chun Huang ,  Chih-Shiang Chou ,  Hsin-Chang Lee ,  Kuei Shun Chen

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F7/70125

Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

Abstract translation: 一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。 该方法还包括执行照明器在光掩模上的曝光。 此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。 此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。 第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。 此外，该方法包括在第二相邻模板中检查第一OPC设置以获得相对较小的EPE，MEEF和DOM与限定的门间距的第一模板的一致性。

公开(公告)号：US08381153B2

公开(公告)日：2013-02-19

申请号：US12884442

申请日：2010-09-17

Applicant: Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J. H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

Inventor： Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J. H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

公开(公告)号：US20120115073A1

公开(公告)日：2012-05-10

申请号：US12940230

申请日：2010-11-05

Applicant: Jeng-Shiun Ho ,  Luke Lo ,  Ting-Chun Liu ,  Min-Hung Cheng ,  Jing-Wei Shih ,  Wen-Han Chu ,  Cheng-Cheng Kuo ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Yu-Hsiang Lin ,  Shang-Yu Huang

Inventor： Jeng-Shiun Ho ,  Luke Lo ,  Ting-Chun Liu ,  Min-Hung Cheng ,  Jing-Wei Shih ,  Wen-Han Chu ,  Cheng-Cheng Kuo ,  Hua-Tai Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Yu-Hsiang Lin ,  Shang-Yu Huang

IPC: G03F1/00

CPC classification number: G03F1/36

Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.

Abstract translation: 本公开提供了一种光掩模。 光掩模包括形成在基板上的第一集成电路（IC）特征; 以及形成在所述基板上并被配置为接近所述第一IC特征的第二IC特征。 第一和第二IC特征定义了具有第一图案密度的致密图案。 第二IC特征从致密图形进一步扩展，形成具有小于第一图案密度的第二图案密度的隔离图案。 从密集图案到隔离图案定义过渡区域。 光掩模还包括形成在基板上的分解杆（SRR），其设置在过渡区域中，并与第一IC特征连接。

公开(公告)号：US20090258302A1

公开(公告)日：2009-10-15

申请号：US12100907

申请日：2008-04-10

Applicant: Jeng-Shiun Ho ,  Jun-Hua Chen ,  Luke Lo ,  Louis Lin ,  Bing-Syun Yeh ,  Cheng-Cheng Kuo ,  Hua-Tai Lin

Inventor： Jeng-Shiun Ho ,  Jun-Hua Chen ,  Luke Lo ,  Louis Lin ,  Bing-Syun Yeh ,  Cheng-Cheng Kuo ,  Hua-Tai Lin

IPC: G03F1/00 ,  G06F17/50

CPC classification number: G03F1/36

Abstract: A photomask including a main feature, corresponding to an integrated circuit feature, and a sub-resolution assist feature (SRAF) is provided. A first imaginary line tangential with a first edge of the main feature and a second imaginary line tangential with the second edge of the main feature define an area adjacent the main feature. A center point of the SRAF lies within this area. The SRAF may be a symmetrical feature. In an embodiment, the center point of the SRAF lies on an imaginary line extending at approximately 45-degree angle from a corner of a main feature.

Abstract translation: 提供了包括对应于集成电路特征的主要特征的光掩模和子分辨率辅助特征（SRAF）。 与主要特征的第一边缘切线的第一虚拟线和与主要特征的第二边缘相切的第二假想线切线限定与主要特征相邻的区域。 SRAF的中心位于该区域内。 SRAF可以是对称的特征。 在一个实施例中，SRAF的中心点位于从主要特征的角度以大约45度角延伸的假想线上。