公开(公告)号：US20130119480A1

公开(公告)日：2013-05-16

申请号：US13294251

申请日：2011-11-11

Applicant: King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

Inventor： King-Yuen Wong ,  Chia-Pin Lin ,  Chia-Yu Lu ,  Yi-Cheng Tsai ,  Da-Wen Lin ,  Kuo-Feng Yu

IPC: H01L29/772 ,  H01L21/02 ,  H01L29/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823437 ,  H01L27/0629 ,  H01L29/66545 ,  H01L29/8605

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract translation: 半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。 触点设置在电阻上。 还提供了一种制造这种半导体器件的方法。

公开(公告)号：US08441107B2

公开(公告)日：2013-05-14

申请号：US13599507

申请日：2012-08-30

Applicant: Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

Inventor： Peng-Soon Lim ,  Chia-Pin Lin ,  Kuang-Yuan Hsu

IPC: H01L29/06

CPC classification number: H01L27/092 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract translation: 一种装置包括第一装置。 第一装置包括第一突起和第一栅极结构，第一突起从衬底向上延伸并且在其中具有第一沟道区域，并且第一栅极结构接合与第一沟道区相邻的第一突起。 第一结构包括在第一通道区域上的开口，以及设置在开口中的具有低电阻率的保形的纯金属。 该装置还包括第二装置，其包括第二突起和第二栅极结构，第二突起从基板向上延伸并且在其中具有第二通道区域，并且第二栅极结构接合与第二通道区域相邻的第二突出部。 第二结构包括设置在第二通道区域上的硅化物，其中硅化物包括设置在开口中的相同金属的金属。

公开(公告)号：US20120086053A1

公开(公告)日：2012-04-12

申请号：US12900626

申请日：2010-10-08

Applicant: Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

Inventor： Chih-Hung TSENG ,  Da-Wen LIN ,  Chien-Tai CHAN ,  Chia-Pin LIN ,  Li-Wen WENG ,  An-Shen CHANG ,  Chung-Cheng WU

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7853

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract translation: 晶体管包括覆盖在浅沟槽隔离层下面的切口鳍。 可以使用一个或多个凹口，其尺寸可以沿翅片的横向方向变化。 在一些实施例中，使用根据硅取向选择性的各向异性湿蚀刻形成凹口。 实例湿蚀刻剂是氢氧化四甲基铵（TMAH）或氢氧化钾（KOH）。

公开(公告)号：US08609495B2

公开(公告)日：2013-12-17

申请号：US12756662

申请日：2010-04-08

Applicant: Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

Inventor： Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极 ，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极， 从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽，并且去除第一和第二沟槽外的金属层。

公开(公告)号：US20120248550A1

公开(公告)日：2012-10-04

申请号：US13077358

申请日：2011-03-31

Applicant: Yu-Lien HUANG ,  Chia-Pin LIN ,  Sheng-Hsiung WANG ,  Fan-Yi HSU ,  Chun-Liang TAI

Inventor： Yu-Lien HUANG ,  Chia-Pin LIN ,  Sheng-Hsiung WANG ,  Fan-Yi HSU ,  Chun-Liang TAI

IPC: H01L29/78 ,  H01L21/26

CPC classification number: H01L27/088 ,  H01L29/513 ,  H01L29/66545

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

Abstract translation: 本文公开的方法和结构的实施例提供了利用掺杂剂围绕栅极结构进行掺杂层间电介质膜ILD0的机制，以在去除伪栅极电极层和/或栅极电介质层的过程中降低其蚀刻速率 替换门技术。 可以用等离子体掺杂工艺（PLAD）或离子束工艺来掺杂ILD0膜。 后掺杂退火是可选的。

公开(公告)号：US08237399B2

公开(公告)日：2012-08-07

申请号：US12547665

申请日：2009-08-26

Applicant: Chia-Pin Lin

Inventor： Chia-Pin Lin

IPC: H02J7/00 ,  H02J7/16

CPC classification number: H02J7/0029 ,  H02J7/0047

Abstract: A system and method of controlling charging process of an electronic device. The electronic device is installed with a battery and a protection circuit. The method includes setting a time interval to check a charging state of the electronic device, checking whether the battery is in an error state before a power supply charges the electronic device, and checking whether the electronic device is in an charging error state according to the time interval till the electronic device completes the charging process. When there is an abnormity, the method can output a message to a user and end the charging process using the protection circuit.

Abstract translation: 一种控制电子设备充电过程的系统和方法。 电子设备安装有电池和保护电路。 该方法包括：设定电子装置的充电状态的时间间隔，在电源对电子装置充电之前检查电池是否处于错误状态，根据电子装置的状态检查电子装置是否处于充电状态 电子设备完成充电过程的时间间隔。 当有异常时，该方法可以向用户输出消息，并使用保护电路结束充电过程。

公开(公告)号：US20110193175A1

公开(公告)日：2011-08-11

申请号：US12711690

申请日：2010-02-24

Applicant: Chih-Hsiang HUANG ,  Chia-Pin LIN

Inventor： Chih-Hsiang HUANG ,  Chia-Pin LIN

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract translation: 集成电路器件包括在半导体衬底上延伸并在第一纵向方向上延伸的栅极区域。 第一翅片具有第一侧壁，其在半导体衬底上方的第二纵向方向上延伸，使得第一鳍片与栅极区域相交。 第二鳍片具有在半导体衬底上方的第二方向上延伸的第二侧壁，使得第二鳍片与栅极区域相交。 在第一和第二鳍片的第一和第二侧壁之间的半导体衬底中形成浅沟槽隔离（STI）区域。 布置在所述第一绝缘层之上和所述第一和第二鳍片的顶表面之上的导电层。 第一绝缘层设置在STI区的上表面和导电层的下表面之间，以将STI区与导电层分离。

公开(公告)号：US20100253291A1

公开(公告)日：2010-10-07

申请号：US12547665

申请日：2009-08-26

Applicant: CHIA-PIN LIN

Inventor： CHIA-PIN LIN

IPC: H02J7/04

CPC classification number: H02J7/0029 ,  H02J7/0047

Abstract: A system and method of controlling charging process of an electronic device. The electronic device is installed with a battery and a protection circuit. The method includes setting a time interval to check a charging state of the electronic device, checking whether the battery is in an error state before a power supply charges the electronic device, and checking whether the electronic device is in an charging error state according to the time interval till the electronic device completes the charging process. When there is an abnormity, the method can output a message to a user and end the charging process using the protection circuit.

Abstract translation: 一种控制电子设备充电过程的系统和方法。 电子设备安装有电池和保护电路。 该方法包括：设定电子装置的充电状态的时间间隔，在电源对电子装置充电之前检查电池是否处于错误状态，根据电子装置的状态检查电子装置是否处于充电状态 电子设备完成充电过程的时间间隔。 当有异常时，该方法可以向用户输出消息，并使用保护电路结束充电过程。

公开(公告)号：US20060255405A1

公开(公告)日：2006-11-16

申请号：US11231624

申请日：2005-09-21

Applicant: Bing-Yue Tsui ,  Chia-Pin Lin

Inventor： Bing-Yue Tsui ,  Chia-Pin Lin

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L21/44

CPC classification number: H01L29/66772 ,  H01L21/28518 ,  H01L21/28537 ,  H01L29/4908

Abstract: The present invention proposes a nano-scale high-performance SOI MOSFET device and a process for manufacturing the same. The device is characterized by comprising: a metal oxide semiconductor, formed on the SOI substrate; a silicide layer (05), wherein a gate consists of a single full silicide gate (10), a high-K dielectric layer (08) and a part for work function modification (09); and source/drain (6) are complete through a silicide reaction and has a modified Schottky junction.

Abstract translation: 本发明提出一种纳米级高性能SOI MOSFET器件及其制造方法。 该器件的特征在于包括：形成在SOI衬底上的金属氧化物半导体; 硅化物层（05），其中栅极由单个完全硅化物栅极（10），高K电介质层（08）和用于功函数修改的部分（09）组成; 并且源极/漏极（6）通过硅化物反应完成并具有改进的肖特基结。

公开(公告)号：US08937353B2

公开(公告)日：2015-01-20

申请号：US12714796

申请日：2010-03-01

Applicant: Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。