公开(公告)号：US20130277750A1

公开(公告)日：2013-10-24

申请号：US13451261

申请日：2012-04-19

Applicant: Jui-Yao Lai ,  Chun-Yi Lee ,  Shyh-Wei Wang ,  Yen-Ming Chen

Inventor： Jui-Yao Lai ,  Chun-Yi Lee ,  Shyh-Wei Wang ,  Yen-Ming Chen

IPC: H01L27/06 ,  H01L27/08

CPC classification number: H01L28/24 ,  H01L21/823842 ,  H01L23/5228 ,  H01L27/0629 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.

公开(公告)号：US20130105204A1

公开(公告)日：2013-05-02

申请号：US13417869

申请日：2012-03-12

Applicant: Jenn-Chang HWANG ,  Chao-Ying HSIEH ,  Chwung-Shan KOU ,  Chung-Hwa WANG ,  Li-Shiuan TSAI ,  Lung-Kai MAO ,  Shih-Jie JIAN ,  Jian-You LIN ,  Chun-Yi LEE

Inventor： Jenn-Chang HWANG ,  Chao-Ying HSIEH ,  Chwung-Shan KOU ,  Chung-Hwa WANG ,  Li-Shiuan TSAI ,  Lung-Kai MAO ,  Shih-Jie JIAN ,  Jian-You LIN ,  Chun-Yi LEE

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K1/0346 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/4676 ,  H05K2203/178 ,  Y10T29/49124

Abstract: A circuit board and a method for manufacturing the same are disclosed. The circuit board of the present invention comprises: a carrier board, wherein a first circuit layer is disposed on at least one surface of the carrier board, and the first circuit layer comprises plural conductive pads; a protein dielectric layer disposed on the surface of the carrier board and the first circuit layer, wherein the protein dielectric layer has plural openings to expose the conductive pads; and a second circuit layer disposed on a surface of the protein dielectric layer, wherein the second circuit layer comprises plural first conductive vias, and each first conductive via is correspondingly formed in the opening and electrically connects to the conductive pad.

Abstract translation: 公开了一种电路板及其制造方法。 本发明的电路板包括：承载板，其中第一电路层设置在载板的至少一个表面上，第一电路层包括多个导电焊盘; 设置在所述载体板和所述第一电路层的表面上的蛋白质电介质层，其中所述蛋白质介电层具有多个开口以暴露所述导电焊盘; 以及设置在所述蛋白质电介质层的表面上的第二电路层，其中所述第二电路层包括多个第一导电通孔，并且每个第一导电通孔相应地形成在所述开口中并且电连接到所述导电焊盘。

公开(公告)号：US20130052813A1

公开(公告)日：2013-02-28

申请号：US13221214

申请日：2011-08-30

Applicant: Ming-Hsi YEH ,  Chun-Yi LEE ,  Chi-Ming YANG ,  Chin-Hsiang LIN

Inventor： Ming-Hsi YEH ,  Chun-Yi LEE ,  Chi-Ming YANG ,  Chin-Hsiang LIN

IPC: H01L21/425

CPC classification number: H01L21/823431 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a method and structure for utilizing advance channel substrate materials in semiconductor manufacturing. Advanced channel substrate materials such as germanium and Group III-V channel substrate materials, are advantageously utilized. One or more capping films including at least a nitride layer are formed over the channel substrate prior to patterning, ion implantation and the subsequent stripping and wet cleaning operations. With the capping layers intact during these operations, attack of the channel substrate material is prevented and the protective films are easily removed subsequently. The films are dimensioned in conjunction with the ion implantation operation to enable the desired dopant profile and concentration to be formed in the channel substrate material.

Abstract translation: 提供了一种在半导体制造中利用前置沟道衬底材料的方法和结构。 可以有利地利用诸如锗和III-V族通道衬底材料的高级通道衬底材料。 在图案化，离子注入和随后的剥离和湿式清洗操作之前，在沟道基底上方形成至少包含至少氮化物层的一个或多个封盖膜。 在这些操作期间，封盖层完好无损，防止了通道衬底材料的侵蚀，随后保护膜很容易被去除。 这些膜的尺寸与离子注入操作相结合，使得能够在通道衬底材料中形成所需的掺杂剂分布和浓度。

公开(公告)号：US20120073629A1

公开(公告)日：2012-03-29

申请号：US12890756

申请日：2010-09-27

Applicant: Woei-yuan Wu ,  Chun-yi Lee

Inventor： Woei-yuan Wu ,  Chun-yi Lee

IPC: H01L31/048 ,  H01L31/18

CPC classification number: H01L31/02013 ,  H02S40/34 ,  Y02E10/50

Abstract: An improved solar cell module and a method of manufacturing the same are disclosed in the invention. The solar cell modules includes: a solar cell matrix, having a number of conductive wires, for transforming solar energy into electric energy to be outputted; a front sheet, formed on one side of the solar cell matrix, for passing solar light; a back sheet, formed on the other side of the solar cell matrix, for passing solar light; and an isolating cover, covering the solar cell matrix, for protecting the solar cell matrix from stress, humidity and heat. A number of holes are formed through the back sheet and the isolating cover, the conductive wires are soldered with insulated cables passing through the holes, and an adhesive is used to seal the hole and fix the cables.

Abstract translation: 本发明公开了一种改进的太阳能电池模块及其制造方法。 太阳能电池模块包括：太阳能电池阵列，具有多个导线，用于将太阳能转换为要输出的电能; 形成在太阳能电池矩阵的一侧的用于通过太阳光的前片; 形成在太阳能电池矩阵的另一侧的用于通过太阳光的背板; 以及覆盖太阳能电池基体的隔离罩，用于保护太阳能电池基体免受应力，湿度和热量的影响。 通过背板和隔离罩形成多个孔，导线通过穿过孔的绝缘电缆焊接，并且使用粘合剂来密封孔并固定电缆。

公开(公告)号：US20110297044A1

公开(公告)日：2011-12-08

申请号：US12951668

申请日：2010-11-22

Applicant: Tsung-Yen TSAI ,  Chun-Yi Lee

Inventor： Tsung-Yen TSAI ,  Chun-Yi Lee

IPC: C04B14/00 ,  C07C211/54

CPC classification number: C04B14/206

Abstract: In an embodiment, an oligoaniline exfoliating agent, as shown in Formula (I), is provided. In Formula (I), R is —H or —NH2, and n is 3 to 30. In another embodiment, exfoliated platelet-shaped clay including the oligoaniline exfoliating agent and a method for preparing the exfoliated platelet-shaped clay are provided.

Abstract translation: 在一个实施方案中，提供如式（I）所示的寡苯胺去角质剂。 在式（I）中，R为-H或-NH 2，n为3至30.在另一个实施方案中，提供了包含低聚苯胺去角质剂的剥离片状粘土和制备剥离的片状粘土的方法。

公开(公告)号：US08041912B2

公开(公告)日：2011-10-18

申请号：US11863254

申请日：2007-09-28

Applicant: Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G06F12/00

CPC classification number: G11C8/20 ,  G06F21/79 ,  G11C16/22

Abstract: A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.

Abstract translation: 存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。 存储器阵列包含被配置为具有独立访问控制的多个存储器块。 状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。 安全寄存器包括至少一个寄存器保护位。 寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。 寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

公开(公告)号：US08040734B2

公开(公告)日：2011-10-18

申请号：US12767418

申请日：2010-04-26

Applicant: Yung-Feng Lin ,  Chun-Yi Lee

Inventor： Yung-Feng Lin ,  Chun-Yi Lee

IPC: G11C11/34

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C16/28 ,  G11C2207/063

Abstract: A sense amplifying method, applied in a memory having a memory cell and a reference cell, includes: charging the memory cell and the reference cell to have a cell current and a reference current, respectively; duplicating the cell current and the reference current to respectively generate a mirrored cell current via a first current path and a mirrored reference current via a second current path and equalizing a first voltage drop generated as the mirrored cell current flows by the first current path and a second voltage drop generated as the mirrored reference current flows by the second current path; and removing the equalization of the first voltage drop and the second voltage drop and adjusting first voltage drop and the second voltage drop according to a first current flowing by the first current path and a second current flowing by the second current path.

Abstract translation: 应用于具有存储单元和参考单元的存储器中的感测放大方法包括：分别对存储单元和参考单元充电以具有单元电流和参考电流; 复制单元电流和参考电流以经由第二电流路径分别经由第一电流路径和镜像参考电流产生镜像单元电流，并且均衡由第一电流路径流动的镜像单元电流产生的第一电压降和 当第二电流路径流过镜像参考电流时产生的第二电压降; 以及去除所述第一电压降和所述第二电压降的均衡，并且根据由所述第一电流路径流动的第一电流和由所述第二电流路径流动的第二电流来调节第一电压降和所述第二电压降。

公开(公告)号：US08035417B1

公开(公告)日：2011-10-11

申请号：US12843452

申请日：2010-07-26

Applicant: Chun-Hsiung Hung ,  Chun-Yi Lee

Inventor： Chun-Hsiung Hung ,  Chun-Yi Lee

IPC: H03K19/094

CPC classification number: H03K19/018521 ,  H03K19/018528

Abstract: An output buffer circuit has a variable output drive strength, depending on a buffer enable signal. Multiple output buffer circuits have a variable combined output drive strength, depending on a set of buffer enable signals.

Abstract translation: 根据缓冲器使能信号，输出缓冲电路具有可变的输出驱动强度。 多个输出缓冲电路具有可变的组合输出驱动强度，这取决于一组缓冲器使能信号。

公开(公告)号：US07908469B2

公开(公告)日：2011-03-15

申请号：US11985149

申请日：2007-11-13

Applicant: Ling-Hung Yu ,  Ying-Chih Lu ,  Chun-Yi Lee ,  Chi-Tsung Chang ,  Meng-Hua Cheng ,  Chun-Lung Wu

Inventor： Ling-Hung Yu ,  Ying-Chih Lu ,  Chun-Yi Lee ,  Chi-Tsung Chang ,  Meng-Hua Cheng ,  Chun-Lung Wu

IPC: G06F9/00 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F15/177

Abstract: A method for executing the power on self test (POST) on the computer system and a method for updating the SMBIOS information partially are provided for a computer system with a first memory and a second memory, wherein the first memory comprises a first storage block and a second storage block. A user can previously set the specific SMBIOS information in the second storage block. And during the POST stage, the default SMBIOS information in the BIOS code loaded from the first storage block to the second memory will be partially updated according to the specific SMBIOS information set by the user. As a result, the purpose of using the appropriated SMBIOS information to initiate the computer system can be achieved.

Abstract translation: 一种用于在计算机系统上执行电源自检（POST）的方法和部分地用于更新SMBIOS信息的方法被提供给具有第一存储器和第二存储器的计算机系统，其中第一存储器包括第一存储块和 第二个存储块。 用户可以预先在第二个存储块中设置特定的SMBIOS信息。 在POST阶段，从第一个存储块加载到第二个存储器的BIOS代码中的默认SMBIOS信息将根据用户设置的特定SMBIOS信息进行部分更新。 因此，可以实现使用专用的SMBIOS信息来启动计算机系统的目的。

公开(公告)号：US20100285643A1

公开(公告)日：2010-11-11

申请号：US12791656

申请日：2010-06-01

Applicant: Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

Inventor： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC: H01L21/8238

CPC classification number: H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract translation: 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。