Patent search ap:"Chung Woo LEE" Page 2

11.

发明授权
Semiconductor chip having bond pads 有权
Title translation: 具有接合垫的半导体芯片

公开(公告)号：US07541682B2

公开(公告)日：2009-06-02

申请号：US11556153

申请日：2006-11-02

Applicant: Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

Inventor： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

IPC: H01L23/48 , H01L23/52 , H01L23/495 , H01L23/525 , H01L25/065

CPC classification number: H01L24/05 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06558 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract translation: 半导体芯片具有一个或多个外围接合焊盘。半导体芯片包括具有彼此相邻的单元区域和外围电路区域的半导体衬底。在半导体衬底的周边区域的至少一部分上形成接合焊盘布线图案。在接合焊盘布线图案和半导体衬底的暴露部分上形成钝化层; 衬垫重排图案，设置在钝化层上并电连接到接合焊盘布线图案; 以及形成在垫重排图案上的绝缘层。绝缘层在其中具有露出焊盘重排图案的一部分以限定接合焊盘的开口。接合焊盘设置在电池区域的至少一部分上。

12.

发明授权
Semiconductor chip having bond pads 有权
Title translation: 具有接合垫的半导体芯片

公开(公告)号：US07453159B2

公开(公告)日：2008-11-18

申请号：US11616857

申请日：2006-12-27

Applicant: Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

Inventor： Young-Hee Song , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

IPC: H01L23/48 , H01L23/495 , H01L23/52 , H01L23/525 , H01L25/065

CPC classification number: H01L24/06 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/02166 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32245 , H01L2224/48 , H01L2224/48091 , H01L2224/48095 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/48227 , H01L2924/00 , H01L2924/00012 , H01L2224/32225 , H01L2224/45099

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract translation: 半导体芯片包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体基板。在半导体衬底上形成接合焊盘布线图形。焊盘重排图案电连接到接合焊盘布线图案。垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。因此，利用本发明的实施例，由此可以大大减小总体芯片尺寸，并且可以制造MCP而没有上述问题。

13.

发明申请
SEMICONDUCTOR CHIP HAVING BOND PADS AND MULTI-CHIP PACKAGE 有权

公开(公告)号：US20070057367A1

公开(公告)日：2007-03-15

申请号：US11556156

申请日：2006-11-02

Applicant: Young-Hee SONG , Il-Heung CHOI , Jeong-Jin KIM , Hae-Jeong SOHN , Chung-Woo LEE

Inventor： Young-Hee SONG , Il-Heung CHOI , Jeong-Jin KIM , Hae-Jeong SOHN , Chung-Woo LEE

IPC: H01L23/34

CPC classification number: H01L24/05 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06558 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

14.

发明申请
Information storage medium and apparatus for reproducing the same 审中-公开
Title translation: 信息存储介质及其再现装置

公开(公告)号：US20070041303A1

公开(公告)日：2007-02-22

申请号：US11483014

申请日：2006-07-10

Applicant: Ji-deog Kim , Chung-woo Lee , Chung-choo Chung , Bong-sik Kwak , Sang-han Lee

Inventor： Ji-deog Kim , Chung-woo Lee , Chung-choo Chung , Bong-sik Kwak , Sang-han Lee

IPC: G11B7/00

CPC classification number: G11B7/0938 , G11B7/0065 , G11B7/00781 , G11B7/083

Abstract: An information storage medium stored hologram data images and an apparatus for reproducing data image from the same are provided. The medium includes a line-type servo image formed on one side of a hologram data image in radial direction. The apparatus includes an information storage medium, the first photodetector, and a signal processor. The first photodetector detects a servo image from the information storage medium and the signal processor generates at least one of a servo control signal and an address signal from a signal detected by the first photodetector.

Abstract translation: 提供存储全息图数据图像的信息存储介质和用于从其再现数据图像的装置。该介质包括在全息图数据图像的一侧沿径向形成的线型伺服图像。该装置包括信息存储介质，第一光电检测器和信号处理器。第一光电检测器从信息存储介质检测伺服图像，并且信号处理器从由第一光电检测器检测的信号中产生伺服控制信号和地址信号中的至少一个。

15.

发明申请
Tracking control method and apparatus and image capture method and apparatus for holographic information recording medium 审中-公开
Title translation: 用于全息信息记录介质的跟踪控制方法和装置以及图像捕获方法和装置

公开(公告)号：US20060133236A1

公开(公告)日：2006-06-22

申请号：US11189726

申请日：2005-07-27

Applicant: Ji-deog Kim , Bong-sik Kwak , Chung-woo Lee , Chung-choo Chung , Sang-han Lee

Inventor： Ji-deog Kim , Bong-sik Kwak , Chung-woo Lee , Chung-choo Chung , Sang-han Lee

IPC: G11B7/00

CPC classification number: G11B7/0938 , G11B7/0065 , G11B7/00781 , G11B7/0901

Abstract: Provided is a method of controlling tracking of an information recording medium including an area for storing a holographic image and an area for storing servo spots formed discretely and at a predetermined interval, which is achieved by obtaining an RF-SUM signal by adding all of detection signals of a quadrant photodetector for detecting the servo spot, monitoring whether the RF-SUM signal exceeds a predetermined level, and performing tracking control in a section where the RF-SUM signal exceeds the predetermined level. Also provided is a related apparatus.

Abstract translation: 提供一种控制信息记录介质的跟踪的方法，该信息记录介质包括用于存储全息图像的区域和用于存储离散形成的并以预定间隔形成的伺服光斑的区域，其通过将所有检测结果相加获得RF-SUM信号来实现用于检测伺服点的象限光电检测器的信号，监视RF-SUM信号是否超过预定电平，并且在RF-SUM信号超过预定电平的部分中执行跟踪控制。还提供了一种相关装置。

16.

发明申请
SEMICONDUCTOR CHIP HAVING BOND PADS 有权
Title translation: 具有粘结垫的半导体芯片

公开(公告)号：US20070108632A1

公开(公告)日：2007-05-17

申请号：US11616850

申请日：2006-12-27

Applicant: Young-Hee SONG , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

Inventor： Young-Hee SONG , Il-Heung Choi , Jeong-Jin Kim , Hae-Jeong Sohn , Chung-Woo Lee

IPC: H01L23/48 , H01L21/44

CPC classification number: H01L24/05 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L23/525 , H01L23/5389 , H01L24/03 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05116 , H01L2224/05118 , H01L2224/05155 , H01L2224/0516 , H01L2224/05554 , H01L2224/05556 , H01L2224/05616 , H01L2224/05618 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/05669 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48235 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/48471 , H01L2224/49113 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2225/06555 , H01L2225/06558 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099

Abstract: In one embodiment, a semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other; a bond pad-wiring pattern formed on at least a part of the peripheral region of the semiconductor substrate; a passivation layer formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.

Abstract translation: 在一个实施例中，半导体芯片具有一个或多个外围接合焊盘。半导体芯片包括具有彼此相邻的单元区域和外围电路区域的半导体衬底; 形成在半导体衬底的周边区域的至少一部分上的接合焊盘布线图案; 形成在所述接合焊盘布线图案上的钝化层和所述半导体基板的暴露部分; 衬垫重排图案，设置在钝化层上并电连接到接合焊盘布线图案; 以及形成在垫重排图案上的绝缘层。绝缘层在其中具有露出焊盘重排图案的一部分以限定接合焊盘的开口。接合焊盘设置在电池区域的至少一部分上。

17.

发明授权
Instant lighting type fluorescent lamp lighting circuit 失效
Title translation: 即时照明型荧光灯照明电路

公开(公告)号：US5734231A

公开(公告)日：1998-03-31

申请号：US698899

申请日：1996-08-16

Applicant: Chung Woo Lee , Yong K. Park

Inventor： Chung Woo Lee , Yong K. Park

IPC: H05B41/24 , H05B41/04 , H05B37/02

CPC classification number: H05B41/046

Abstract: A fluorescent lamp lighting circuit is disclosed in which an instant lighting is possible, and a high reliability is ensured. Further, the circuit is compact, and the cost is low. The fluorescent lamp lighting circuit according to the present invention includes a discharge circuit section including a choke coil serially connected to a filament of a fluorescent lamp. It further includes a lighting circuit section connected serially to the filament and the choke coil so as to be turned on at certain intervals by supplying the power, and so as to be turned off after the starting of the glow discharge of the fluorescent lamp. It further includes a protecting circuit section for turning off the light circuit section after certain repetition of on/off operations of the lighting circuit section.

Abstract translation: 公开了一种荧光灯照明电路，其中即时照明是可能的，并且确保了高可靠性。此外，电路紧凑，成本低。根据本发明的荧光灯点亮电路包括放电电路部分，其包括串联连接到荧光灯的灯丝的扼流线圈。它还包括一个点亮电路部分，其串联连接到灯丝和扼流线圈，以便通过提供电源以一定的间隔被接通，并且在荧光灯的辉光放电开始之后被关闭。其还包括保护电路部分，用于在点亮电路部分的某些重复的开/关操作之后关闭光电路部分。

18.

发明申请
ELECTRIC VEHICLE, ELECTRIC-VEHICLE CHARGING STAND AND COMMUNICATION SYSTEM THEREBETWEEN 有权
Title translation: 电动车辆，电动车辆充电站和通讯系统

公开(公告)号：US20120200258A1

公开(公告)日：2012-08-09

申请号：US13241135

申请日：2011-09-22

Applicant: CHUNG WOO LEE

Inventor： CHUNG WOO LEE

IPC: H02J7/00

CPC classification number: B60L11/1825 , B60L11/1838 , H02J7/0004 , Y02T10/7005 , Y02T10/7072 , Y02T90/121 , Y02T90/128 , Y02T90/14 , Y02T90/16 , Y02T90/163

Abstract: Disclosed are an electric vehicle (EV), an EV charging stand, and a communication system therebetween, the EV including a charge control unit configured to detect a preparation state for charging a battery and output a resistance varying signal according to the detected state, and a resistor unit configured to vary a resistance value in response to the resistance varying signal, thus changing a voltage value of a state signal transmitted to the EV charging stand, and the EV charging stand including a comparator configured to receive a stage signal from the EV, compare a voltage value of the received state signal with a reference value, and output a signal in response to a result of comparing, and a control unit configured to receive the signal from the comparator and detect a preparation state for charging the battery of the EV.

Abstract translation: 公开了一种电动车辆（EV），EV充电座及其间的通信系统，所述EV包括充电控制单元，其被配置为检测用于对电池充电的准备状态并根据检测到的状态输出电阻变化信号，以及电阻单元，被配置为响应于电阻变化信号而改变电阻值，从而改变发送到EV充电座的状态信号的电压值，并且EV充电座包括比较器，其被配置为从EV接收级信号将接收到的状态信号的电压值与参考值进行比较，并且响应于比较结果输出信号;以及控制单元，被配置为从比较器接收信号，并检测用于对电池进行充电的准备状态电动汽车