公开(公告)号：US07364957B2

公开(公告)日：2008-04-29

申请号：US11490012

申请日：2006-07-20

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/331

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

公开(公告)号：US07332756B2

公开(公告)日：2008-02-19

申请号：US11285524

申请日：2005-11-21

Applicant: Chung Long Cheng ,  Kong-Beng Thei ,  Harry Haklay Chuang

Inventor： Chung Long Cheng ,  Kong-Beng Thei ,  Harry Haklay Chuang

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/70

CPC classification number: H01L27/0629 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/78

Abstract: A semiconductor structure having a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. The structure includes a first dielectric layer having a first opening and a second opening formed on the semiconductor substrate, and one or more sidewall spacers formed on inner sides of the first opening, in which a portion of the semiconductor substrate is exposed. In addition, the structure includes a coating layer formed on inner sides and a bottom surface of the second opening, a damascene gate structure surrounded by the sidewall spacers formed in the first opening, and a resistive device formed on the coating layer in the second opening.

Abstract translation: 公开了一种在半导体衬底上具有镶嵌栅极结构和电阻器件的半导体结构。 该结构包括具有形成在半导体衬底上的第一开口和第二开口的第一电介质层，以及形成在第一开口的内侧上的一个或多个侧壁间隔物，半导体衬底的一部分露出。 此外，该结构包括形成在第二开口的内侧和底面上的涂层，由形成在第一开口中的侧壁隔离物包围的镶嵌栅极结构，以及形成在第二开口中的涂层上的电阻元件 。

公开(公告)号：US20080001188A1

公开(公告)日：2008-01-03

申请号：US11477953

申请日：2006-06-30

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC: H01L29/76 ,  H01L21/8234

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

Abstract: Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

Abstract translation: 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20060115947A1

公开(公告)日：2006-06-01

申请号：US11334974

申请日：2006-01-18

Applicant: Chung-Long Cheng ,  Kong-Beng Thei

Inventor： Chung-Long Cheng ,  Kong-Beng Thei

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/66795

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

公开(公告)号：US20050260827A1

公开(公告)日：2005-11-24

申请号：US10850747

申请日：2004-05-20

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

IPC: H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/469 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/76224

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract translation: 一种在表面特别是硅表面上清洗和形成氧化膜的方法。 表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。 该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

公开(公告)号：US20050258476A1

公开(公告)日：2005-11-24

申请号：US10851376

申请日：2004-05-21

Applicant: Chung-Long Cheng ,  Kong-Beng Thei

Inventor： Chung-Long Cheng ,  Kong-Beng Thei

IPC: H01L21/3213 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/66795

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract translation: 用于形成FIN-FET器件的方法使用形成在覆盖的地形栅电极材料层上的覆盖平坦化层。 图案化覆盖层平坦化层并用作掩模层，用于图案化覆盖层形成的栅电极材料层以形成栅电极。 由于覆盖平坦化层形成为平坦化层，所以在其上形成的光致抗蚀剂层以更高的分辨率形成。 结果，栅电极也形成了增强的分辨率。 所得到的FIN-FET结构具有在栅电极上以倒U形形成的图案化平坦化层。

公开(公告)号：US08461629B2

公开(公告)日：2013-06-11

申请号：US13178755

申请日：2011-07-08

Applicant: Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

Inventor： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract translation: 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US20120196434A1

公开(公告)日：2012-08-02

申请号：US13443550

申请日：2012-04-10

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L21/02

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US07998830B2

公开(公告)日：2011-08-16

申请号：US12961167

申请日：2010-12-06

Applicant: Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

Inventor： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC: H01L21/76

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract translation: 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US07898037B2

公开(公告)日：2011-03-01

申请号：US11833128

申请日：2007-08-02

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。