公开(公告)号：US08350298B2

公开(公告)日：2013-01-08

申请号：US12810619

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/12 ,  H01L21/00 ,  H01L21/84 ,  H01L27/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US08264863B2

公开(公告)日：2012-09-11

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US20120025267A1

公开(公告)日：2012-02-02

申请号：US13128439

申请日：2010-09-07

申请人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

发明人： Xiaolu Huang ,  Jing Chen ,  Xi Wang ,  Deyuan Xiao

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/78612

摘要： A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.

摘要翻译： 公开了一种用于消除浮体效应和自发热效应的SOI MOS器件。 该器件包括将有源栅极沟道耦合到Si衬底的连接层。 连接层在设备操作期间提供电气和热通道，可以消除浮体效应和自热效应。 详细公开了在Si活性通道和Si衬底之间具有SiGe连接器的MOS器件的实例，并提供了制造工艺。

公开(公告)号：US20110248354A1

公开(公告)日：2011-10-13

申请号：US12810619

申请日：2010-02-11

申请人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

发明人： Deyuan Xiao ,  Xi Wang ,  Miao Zhang ,  Jing Chen ,  Zhongying Xue

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/42392 ,  H01L29/78696

摘要： A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects.

摘要翻译： Ge和Si混合材料反转模式GAA（Gate-All-Around）CMOSFET包括具有第一沟道的PMOS区域，具有第二沟道的NMOS区域和栅极区域。 第一通道和第二通道具有跑道形横截面并分别由n型Ge和p型Si形成; 第一通道和第二通道的表面基本上被栅极区域包围; 在PMOS区域和NMOS区域之间以及在PMOS或NMOS区域和Si衬底之间设置掩埋氧化物层以将它们彼此隔离。 在反相模式下，器件具有混合材料，GAA结构，具有跑道形，高k栅介质层和金属栅极，从而实现高载流子迁移率，防止多晶硅栅极耗尽和短沟道效应。

公开(公告)号：US20110084328A1

公开(公告)日：2011-04-14

申请号：US12886534

申请日：2010-09-20

申请人： DEYUAN XIAO

发明人： DEYUAN XIAO

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881

摘要： A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures.

摘要翻译： 制造非易失性存储器件的方法提供了包括覆盖在表面区域上的表面区域和隧道电介质层的半导体衬底。 优选地，隧道介电层是高K电介质，其特征在于高于3.9的介电常数。 该方法在半导体衬底的第二部分内的第一部分和漏极区域内形成源极区域。 该方法包括在源极区和漏极区之间形成覆盖第一和第二部分的第一和第二纳米晶体硅结构，以形成第一和第二浮栅结构，同时保持第一和第二纳米晶硅结构之间的间隔。 该方法包括形成覆盖第一和第二浮栅结构的第二介质层。 该方法还包括形成覆盖第一和第二浮栅结构的控制栅极结构。

公开(公告)号：US20110063888A1

公开(公告)日：2011-03-17

申请号：US12861622

申请日：2010-08-23

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US20070287246A1

公开(公告)日：2007-12-13

申请号：US11377236

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Seng ,  Roger Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

摘要： A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface.

摘要翻译： 一种用于制造具有至少两个栅极区域的半导体器件的方法。 该方法包括提供包括表面的基底区域。 另外，该方法包括通过至少将第一多个离子注入到衬底区域中并且通过至少将第二多个离子注入衬底区域而在衬底区域中形成漏极区域来在衬底区域中形成源极区域。 漏极区域和源极区域彼此分离。 此外，该方法包括在表面上沉积栅极层，并在表面上形成第一栅极区域和第二栅极区域。

公开(公告)号：US08937322B2

公开(公告)日：2015-01-20

申请号：US13129386

申请日：2010-12-31

申请人： Richard Rugin Chang ,  Deyuan Xiao

发明人： Richard Rugin Chang ,  Deyuan Xiao

IPC分类号： H01L27/15 ,  H01L33/38 ,  H01L33/20 ,  H01L33/46

CPC分类号： H01L33/382 ,  H01L33/20 ,  H01L33/38 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0091

摘要： The present invention provides an LED and the manufacturing method thereof, and a light emitting device. The LED includes a first electrode, for connecting the LED to a negative electrode of a power supply; a substrate, located on the first electrode; and an LED die, located on the substrate; in which a plurality of contact holes are formed extending through the substrate, the diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes: forming successively an LED die and a second electrode on a substrate; patterning a backsurface of the substrate to form inverted trapezoidal contact holes which expose the LED die; and filling the contact holes with conductive material till the backface of the substrate is covered by the conductive material. The LED has a high luminous efficiency and the manufacturing method is easy to implement.

摘要翻译： 本发明提供一种LED及其制造方法以及发光装置。 LED包括用于将LED连接到电源的负极的第一电极; 位于所述第一电极上的衬底; 和位于基板上的LED管芯; 其中形成有多个接触孔延伸穿过衬底，接触孔的上部的直径小于接触孔的下部的直径，并且接触孔填充有将第一电极连接到 LED模具。 发光装置包括LED，并且还包括安装在基座上的基座和LED。 该制造方法包括：在基板上依次形成LED芯片和第二电极; 图案化衬底的后表面以形成露出LED管芯的倒梯形接触孔; 并且用导电材料填充接触孔，直到衬底的背面被导电材料覆盖。 LED的发光效率高，制造方法易于实现。

公开(公告)号：US08614487B2

公开(公告)日：2013-12-24

申请号：US11377936

申请日：2006-03-15

申请人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

发明人： Deyuan Xiao ,  Gary Chen ,  Tan Leong Seng ,  Roger Lee

IPC分类号： H01L29/66

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/66484 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device with at least two gate regions. The device includes a substrate region including a surface, a source region in the substrate region, and a drain region in the substrate region. The drain region and the source region are separate from each other. Additionally, the device includes a first gate region on the surface, a second gate region on the surface, and an insulation region on the surface and between the first gate region and the second gate region. The first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region. The first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region. The second channel is from the source region to the drain region.

摘要翻译： 具有至少两个栅极区域的半导体器件。 该器件包括：衬底区域，其包括表面，衬底区域中的源极区域和衬底区域中的漏极区域。 漏极区域和源极区域彼此分离。 此外，该器件包括表面上的第一栅极区域，表面上的第二栅极区域以及表面上以及第一栅极区域和第二栅极区域之间的绝缘区域。 第一栅极区域和第二栅极区域被绝缘区域分开。 第一栅极区域能够在衬底区域中形成第一沟道。 第一通道从源极区域到漏极区域。 第二栅极区域能够在衬底区域中形成第二沟道。 第二通道从源极区域到漏极区域。

公开(公告)号：US20130207118A1

公开(公告)日：2013-08-15

申请号：US13059633

申请日：2010-12-30

申请人： Deyuan Xiao ,  Richard Rujin Chang

发明人： Deyuan Xiao ,  Richard Rujin Chang

IPC分类号： H01L33/58

CPC分类号： H01L33/58 ,  H01L33/20 ,  H01L2224/14 ,  H01L2224/16225

摘要： The present invention discloses an LED and its fabrication method. The LED comprises: a substrate; an epitaxial layer, an active layer and a capping layer arranged on the substrate in sequence; wherein a plurality of bifocal microlens structures are formed on the surface of the substrate away from the epitaxial layer. When the light emitted from the active layer passes through the surfaces of the bifocal microlens structures, the incident angle is always smaller than the critical angle of total reflection, thus preventing total reflection and making sure that most of the light pass through the surfaces of the bifocal microlens structures, in this way improving external quantum efficiency of the LED, avoiding the rise of the internal temperature of the LED and improving the performance of the LED.

摘要翻译： 本发明公开了一种LED及其制造方法。 LED包括：基板; 一个外延层，一个活性层和一个覆盖层，依次排列在基片上; 其中在所述衬底的表面上远离所述外延层形成多个双焦点微透镜结构。 当从有源层发射的光穿过双焦微透镜结构的表面时，入射角度总是小于全反射的临界角，从而防止全反射，并确保大部分光通过 双焦微透镜结构，以这种方式提高LED的外部量子效率，避免了LED内部温度的升高，并提高了LED的性能。