公开(公告)号：US10364140B2

公开(公告)日：2019-07-30

申请号：US14861886

申请日：2015-09-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lianjun Liu ,  David J. Monk

IPC: B81B7/00 ,  B81C1/00 ,  H01L43/02 ,  H01L43/12 ,  G01L9/00

Abstract: In some embodiments a method of manufacturing a sensor system can comprise forming a first structure having a substrate layer and a first sensor that is positioned on a first side of the substrate layer, bonding a cap structure over the first sensor on the first side of the substrate layer, and depositing a first dielectric layer over the cap structure. After bonding the cap structure and depositing the first dielectric layer, a second sensor is fabricated on the first dielectric layer. The second sensor includes material that would be adversely affected at a temperature that is used to bond the cap structure to the first side of the substrate layer.

公开(公告)号：US10336606B2

公开(公告)日：2019-07-02

申请号：US15053456

申请日：2016-02-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Qing Zhang ,  Mohommad Choudhuri ,  Gul Zeb

IPC: H01L27/14 ,  H01L27/085 ,  B81B7/00 ,  B81C1/00 ,  G01N27/22

Abstract: A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

公开(公告)号：US10324723B2

公开(公告)日：2019-06-18

申请号：US14321957

申请日：2014-07-02

Applicant: Freescale Semiconductor Inc.

Inventor： Peter J Wilson ,  Brian C Kahne ,  Jeffrey W Scott

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

公开(公告)号：US10261924B2

公开(公告)日：2019-04-16

申请号：US15227834

申请日：2016-08-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Hemant Nautiyal ,  Rajan Kapoor ,  Arvind Kaushik ,  Puneet Khandelwal

IPC: G06F13/24 ,  G06F13/42

Abstract: A communication system for communicating control data between a processor and an interface includes configuration registers, a packet processor, an interrupt processor, a timing monitor, a configuration sampler, a control-frame processor, a mode selector, and a transceiver. The processor, timing monitor, and configuration sampler generate control data, a timing signal and frame structure data, respectively. The packet processor generates a transmit control configuration packet, which includes the control data. The control-frame processor inserts the transmit control configuration packet into a first control frame, outputs the control frame to the interface and extracts a receive-configuration packet from a second control frame for generating one or more interrupts. The mode selector generates mode and idle signals for determining the mode of the interface, based on the idle signal. In one implementation, the system uses JESD control frames to reduce GPIO pin usage.

公开(公告)号：US10242955B2

公开(公告)日：2019-03-26

申请号：US15250644

申请日：2016-08-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Mohit Arora ,  Kumar Abhishek ,  Prashant Bhargava ,  Rakesh Pandey

IPC: H01L23/00 ,  G01R31/02 ,  G06F21/87 ,  H03K3/0233 ,  H03K3/84 ,  H03K19/003 ,  H05K1/02

Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

公开(公告)号：US10236260B2

公开(公告)日：2019-03-19

申请号：US15199838

申请日：2016-06-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Michael B. Vincent ,  Gregory J. Durnan

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

Abstract: A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

公开(公告)号：US10212141B2

公开(公告)日：2019-02-19

申请号：US15297332

申请日：2016-10-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Andrei Catalin Frincu ,  George Bogdan Alexandru

IPC: H04L29/06

Abstract: Various embodiments described herein relate to network key manager which is configured to manage keys in nodes in the network, wherein the network key manager including a memory configured to store an update data structure; a processor configured to: determine which nodes are blacklisted; generate the update data structure of volatile private keys for each node that is not blacklisted, wherein the volatile private key is based upon secret information associated with the node and an index, wherein the volatile private key is used for the indexth key update; determine a neighbor node of the network key manager; remove the volatile private key for the neighbor node from the update data structure; encrypt the resulting update data structure and a new network key with the private key for the neighbor node to produce an encrypted message; and send the encrypted message to the neighbor node.

公开(公告)号：US10211058B2

公开(公告)日：2019-02-19

申请号：US14846168

申请日：2015-09-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Jean-Phillippe Laine ,  Patrice Besse ,  Changsoo Hong ,  Rouying Zhan

IPC: H01L27/00 ,  H01L21/00 ,  H01L21/266 ,  H01L27/082 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02

Abstract: An electrostatic discharge protection device includes a buried layer having a plurality of heavily doped regions of a first conductivity type and a laterally diffused region between adjacent heavily doped regions, a semiconductor region over the buried layer, and a first well of the first conductivity type extending from a surface of the semiconductor region to a heavily doped region. The device includes a first transistor in the semiconductor region having an emitter coupled to the first terminal, and a second transistor in the semiconductor region having an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor.

公开(公告)号：US10209070B2

公开(公告)日：2019-02-19

申请号：US15172429

申请日：2016-06-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Aaron A. Geisberger

IPC: G01C19/574 ,  G01C19/5747

Abstract: A microelectromechanical system (MEMS) gyroscope device includes a substrate having a surface parallel to a plane; first and second proof masses driven to slide back and forth past one another in a first directional axis of the plane, where the first and second proof masses respectively have a first and second recess in a respective side closest to the other proof mass; a pivot structure coupled to the first proof mass within the first recess and to the second proof mass within the second recess; an anchor between the first and second recesses and coupled to a mid-point of the pivot structure; and third and fourth proof masses driven to move toward and away from one another in a second directional axis of the plane that is perpendicular to the first directional axis; where the proof masses move in response to angular velocity in one or more directional axes.

公开(公告)号：US10180925B2

公开(公告)日：2019-01-15

申请号：US15081944

申请日：2016-03-28

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Rajan Srivastava ,  Girraj K. Agrawal

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/16

Abstract: An integrated circuit (IC) having multiple cores controls write access to its input/output (I/O) pins. The IC includes a pin-control circuit, a memory, and a set of I/O pins. The pin-control circuit allows a core to independently control individual ones of the I/O pins. A set of pin-control values are defined that correspond to the set of I/O pins to indicate a type of core that can access an I/O pin. The pin-control circuit receives the pin-control values, a source ID, and write data generated by a core, and updates a pin data bit stored in the memory with a corresponding bit of the write data when the core is allowed to access the I/O pin. The pin-control circuit does not change the pin data bit when the core is denied write access to the I/O pin.