中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.012 seconds)

    A SEALING STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    12.
    发明申请
    A SEALING STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
    密封结构及其制造方法

    公开(公告)号：US20100052081A1

    公开(公告)日：2010-03-04

    申请号：US12515590

    申请日：2007-11-15

    Applicant: Johannes Donkers ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Gerhard Koops

    Inventor： Johannes Donkers ,  Erwin Hijzen ,  Philippe Meunier-Beillard ,  Gerhard Koops

    IPC: H01L29/84 ,  H01L21/306

    CPC classification number: B81C1/00293 ,  B81B2201/0271 ,  B81C2203/0145

    Abstract: A method of manufacturing a structure (1100), the method comprising forming a cap element (401) on a substrate (101), removing material (103) of the substrate (101) below the cap element (401) to thereby form a gap (802) between the cap element (401) and the substrate (101), and rearranging material of the cap element (401) and/or of the substrate (101) to thereby merge the cap element (401) and the substrate (101) to bridge the gap (802).

    Abstract translation: 一种制造结构（1100）的方法，所述方法包括在基板（101）上形成盖元件（401），在盖元件（401）下方去除基板（101）的材料（103），从而形成间隙 （401）和基板（101）之间的盖（802）和盖元件（401）和/或基板（101）的重新排列材料，从而合并盖元件（401）和基板（101） ）弥合差距（802）。

    METHOD OF MANUFACTURING A DEVICE WITH A CAVITY
    13.
    发明申请
    METHOD OF MANUFACTURING A DEVICE WITH A CAVITY 有权
    用CAVITY制造器件的方法

    公开(公告)号：US20090267166A1

    公开(公告)日：2009-10-29

    申请号：US12427797

    申请日：2009-04-22

    Applicant: Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

    Inventor： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

    IPC: H01L29/84 ,  H01L21/50

    CPC classification number: H02N1/00 ,  B81C1/00476 ,  H01L21/02 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/50 ,  H01L21/7688 ,  H01L29/84

    Abstract: The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide region (20, 107, 115) with a porous layer (40, 114, 124) being permeable to a vapor HF etchant (100), and C) selectively etching the sacrificial oxide region (20, 107, 115) through the porous layer (40, 114, 124) using the vapor HF etchant (100) to obtain the cavity (50). This method may be used in the manufacture of various micro-devices with a cavity (50), i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

    Abstract translation: 本发明涉及具有空腔（50）的微器件，该微器件包括衬底（10,110），该方法包括以下步骤：A）提供具有表面的衬底（10,110），其包括 在表面（）处的牺牲氧化物区域（20,107,115）; B）用可透气体HF蚀刻剂（100）的多孔层（40,114,124）覆盖所述牺牲氧化物区域（20,107,115），以及C）选择性地蚀刻所述牺牲氧化物区域（20,107,115） 115）通过使用蒸汽HF蚀刻剂（100）的多孔层（40,114,124）获得空腔（50）。 该方法可以用于制造具有空腔（50）的各种微器件，即MEMS器件，特别是其封装部分，以及半导体器件，特别是其BEOL部分。

    POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF
    17.
    发明申请
    POWER SEMICONDUCTOR DEVICE STRUCTURE FOR INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF 审中-公开
    用于集成电路的功率半导体器件结构及其制造方法

    公开(公告)号：US20100244125A1

    公开(公告)日：2010-09-30

    申请号：US12294820

    申请日：2007-03-26

    Applicant: Jan Sonsky ,  Gerhard Koops ,  Rob Van Dalen

    Inventor： Jan Sonsky ,  Gerhard Koops ,  Rob Van Dalen

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/407 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7824 ,  H01L29/7825

    Abstract: A power semiconductor device comprises a conductive gate, provided in an upper part of a trench (11) formed in a semiconductor substrate (1), and a conductive field plate, extending in the trench, parallel to the conductive gate, to a depth greater that the conductive gate. The field plate is insulated from the walls and bottom of the trench by a field plate insulating layer that is thicker than the gate insulating layer. In one embodiment, the field plate is insulated within the trench from the gate. Impurity doped regions of a first conductivity type are provided at the surface of the substrate adjacent the first and second sides of the trench and form source and drain regions, and a body region (7) of second conductivity type is formed under the source region on the first side of the trench (11). The conductive gate is insulated from the body region (7) by a gate insulating layer. A method of making the semiconductor device is compatible with conventional CMOS processes.

    Abstract translation: 功率半导体器件包括导电栅极，其设置在形成于半导体衬底（1）中的沟槽（11）的上部，以及导电场板，其在沟槽中平行于导电栅极延伸到更大的深度 导电门。 场板通过比栅极绝缘层厚的场板绝缘层与沟槽的壁和底部绝缘。 在一个实施例中，场板在与栅极沟槽内绝缘。 第一导电类型的杂质掺杂区域设置在与沟槽的第一和第二侧相邻的衬底的表面处并形成源极和漏极区域，并且在源极区域下方形成第二导电类型的体区域（7） 沟槽（11）的第一侧。 导电栅极通过栅极绝缘层与体区（7）绝缘。 制造半导体器件的方法与常规CMOS工艺兼容。

    MEMS devices
    19.
    发明授权
    MEMS devices 有权
    MEMS器件

    公开(公告)号：US08980698B2

    公开(公告)日：2015-03-17

    申请号：US13128202

    申请日：2009-11-10

    Applicant: Greja Johanna Adriana Verheijden ,  Gerhard Koops

    Inventor： Greja Johanna Adriana Verheijden ,  Gerhard Koops

    IPC: H01L21/00 ,  B81C1/00

    CPC classification number: B81C1/00333 ,  B81C2203/0136 ,  B81C2203/0145

    Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element 14. A sacrificial layer 20 is provided over the device element and a package cover layer 24 is provided over the sacrificial layer. A spacer layer 13 is formed over the sacrificial layer and is etched to define spacer portions adjacent an outer side wall of the sacrificial layer. These improve the hermetic sealing of the side walls of the cover layer 24.

    Abstract translation: 制造MEMS器件的方法包括形成MEMS器件元件14.牺牲层20设置在器件元件上方，并且封装覆盖层24设置在牺牲层上。 间隔层13形成在牺牲层之上并被蚀刻以限定邻近牺牲层的外侧壁的间隔部分。 这些改善了覆盖层24的侧壁的气密密封。

    INTERFACE FOR COMMUNICATION BETWEEN VOLTAGE DOMAINS
    20.
    发明申请
    INTERFACE FOR COMMUNICATION BETWEEN VOLTAGE DOMAINS 有权
    电压域之间的通信接口

    公开(公告)号：US20130281033A1

    公开(公告)日：2013-10-24

    申请号：US13454815

    申请日：2012-04-24

    Applicant: Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

    Inventor： Peter Gerard Steeneken ,  Maarten Jacobus Swanenberg ,  Henk Boezen ,  Gerhard Koops ,  Frans Bontekoe ,  Reinout Woltjer

    IPC: H04B1/44

    CPC classification number: H04B1/44 ,  H03K17/00

    Abstract: One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.

    Abstract translation: 一个或多个实施例提供用于使用电容耦合在不同电压域中工作的电路之间的信号的隔离和通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个电容结构被实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。

Patent Agency Ranking