公开(公告)号：US06366513B1

公开(公告)日：2002-04-02

申请号：US09483381

申请日：2000-01-12

Applicant: Guowei Wang

Inventor： Guowei Wang

IPC: G11C708

CPC classification number: G11C7/062 ,  G11C7/067

Abstract: A memory integrated circuit (100) includes a core cell array (102) having a plurality of core cells for storing data in one of a plurality of states, a plurality of power supply buses (140, 142, 144, 146) including a sensing power supply bus (144) and a sensing ground bus (146) dedicated to sensing states of core cells. The integrated circuit firther includes a sense threshold generating circuit (126) which generates a sense threshold signal in response to a power supply potential on the sensing power supply bus and a ground potential of the sensing ground bus. The integrated circuit still further includes a plurality of sense amplifiers (108) which detect the states of core cells in relation to the sense threshold signal. The sense amplifiers are coupled to the sensing power supply bus and the sensing ground bus so that substantially all power supply noise at the plurality of sense amplifiers and the sense threshold generator is common node noise.

Abstract translation: 存储器集成电路（100）包括具有多个核心单元的核心单元阵列（102），用于以多个状态之一存储数据;多个电源总线（140,142,144,146），包括感测 电源总线（144）和专用于感测核心单元的状态的感测接地总线（146）。 集成电路包括感测阈值产生电路（126），其响应于感测电源总线上的电源电位和感测接地总线的接地电位而产生感测阈值信号。 集成电路还包括多个读出放大器（108），其检测与感测阈值信号相关的核心单元的状态。 感测放大器耦合到感测电源总线和感测接地总线，使得多个感测放大器和感测阈值发生器处的基本上所有的电源噪声都是公共节点噪声。

公开(公告)号：US08462564B1

公开(公告)日：2013-06-11

申请号：US13090981

申请日：2011-04-20

Applicant: Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

Inventor： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC: G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C5/145 ,  G11C8/08

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract translation: 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US08358543B1

公开(公告)日：2013-01-22

申请号：US11229529

申请日：2005-09-20

Applicant: Guowei Wang ,  Sachit Chandra ,  Nian Yang

Inventor： Guowei Wang ,  Sachit Chandra ,  Nian Yang

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/06 ,  G11C16/12

Abstract: Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.

Abstract translation: 用于对诸如闪存之类的非易失性存储器件进行编程的技术包括基于正被编程到存储器件的数据模式的存储器单元的浮动源线。 选择浮置的源极线使得排列位线和行中的不同存储器单元的源位线之间的距离最大化。 以这种方式，可以减小这些漏极位线和源极线之间的漏电流。

公开(公告)号：US07986562B2

公开(公告)日：2011-07-26

申请号：US12650118

申请日：2009-12-30

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20090161462A1

公开(公告)日：2009-06-25

申请号：US11963508

申请日：2007-12-21

Applicant: Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

Inventor： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC: G11C7/02

CPC classification number: G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

Abstract: A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Abstract translation: 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US6125055A

公开(公告)日：2000-09-26

申请号：US421105

申请日：1999-10-19

Applicant: Yasushi Kasa ,  Guowei Wang

Inventor： Yasushi Kasa ,  Guowei Wang

IPC: G11C8/12 ,  G11C15/04 ,  G11C16/22 ,  G11C16/04

CPC classification number: G11C8/12 ,  G11C15/046 ,  G11C16/22

Abstract: A simultaneous operation flash memory capable of write protecting predetermined sectors in the simultaneous operation flash memory. The preferred simultaneous operation flash memory includes a plurality of sectors divided into an upper bank and a sliding lower bank. Each bank is associated with a predetermined amount of sectors in the simultaneous operation flash memory. The simultaneous operation flash memory also includes at least one upper address decoder circuit that has a upper sector select line. During operation, each upper address decoder circuit generates a predetermined output signal on the upper sector select line when selected. In addition, the simultaneous operation flash memory includes at least one lower address decoder circuit including a lower address sector select line, wherein each upper address decoder circuit generates a predetermined output signal on the lower sector select line when selected during operation. Finally, at least one write protect CAM is electrically connected with a respective upper sector select line or a respective lower sector select line, wherein said write protect CAM generates a sector protect signal if the write protect CAM is selected by the respective upper sector select line or the respective lower sector select line.

Abstract translation: 一种同时操作的闪速存储器，其能够写入保护同时操作闪速存储器中的预定扇区。 优选的同时操作闪速存储器包括被划分为上部存储体和滑动式下部存储体的多个扇区。 每个存储体与同步操作闪速存储器中的预定量的扇区相关联。 同时运行的闪速存储器还包括具有上扇区选择线的至少一个高地址解码器电路。 在操作期间，每个高地址解码器电路在选择时在上扇区选择线上产生预定的输出信号。 此外，同时操作闪速存储器包括至少一个下位地址解码器电路，其包括较低地址扇区选择线，其中每个上位地址解码器电路在操作期间选择时在下扇区选择线上产生预定的输出信号。 最后，至少一个写保护CAM与相应的上扇区选择线或相应的下扇区选择线电连接，其中如果写保护CAM由相应的上扇区选择线选择，则所述写保护CAM产生扇区保护信号 或相应的下扇区选择线。

公开(公告)号：US07804715B2

公开(公告)日：2010-09-28

申请号：US12114966

申请日：2008-05-05

Applicant: Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

Inventor： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC: G11C16/06

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

Abstract translation: 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US07345916B2

公开(公告)日：2008-03-18

申请号：US11423638

申请日：2006-06-12

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070291550A1

公开(公告)日：2007-12-20

申请号：US11423638

申请日：2006-06-12

Applicant: Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

Inventor： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC: G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G11C7/00 ,  G11C16/06

CPC classification number: G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07295475B2

公开(公告)日：2007-11-13

申请号：US11229664

申请日：2005-09-20

Applicant: Takao Akaogi ,  Guowei Wang

Inventor： Takao Akaogi ,  Guowei Wang

IPC: G11C11/34

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/10

Abstract: Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.