公开(公告)号：US07957204B1

公开(公告)日：2011-06-07

申请号：US11229667

申请日：2005-09-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

摘要翻译： 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US08462564B1

公开(公告)日：2013-06-11

申请号：US13090981

申请日：2011-04-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Sachit Chandra ,  Aaron Lee

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C8/08

摘要： A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

摘要翻译： 非易失性存储器件包括非易失性存储器单元阵列。 当对存储器单元进行编程时，使用包括多个独立电荷泵的电压源。 独立电荷泵将编程电压提供给存储器单元阵列中的不同位线。 使用多个电荷泵倾向于降低输出电压波动，从而降低功率损耗。

公开(公告)号：US08358543B1

公开(公告)日：2013-01-22

申请号：US11229529

申请日：2005-09-20

申请人： Guowei Wang ,  Sachit Chandra ,  Nian Yang

发明人： Guowei Wang ,  Sachit Chandra ,  Nian Yang

IPC分类号： G11C16/00 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/12

摘要： Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.

摘要翻译： 用于对诸如闪存之类的非易失性存储器件进行编程的技术包括基于正被编程到存储器件的数据模式的存储器单元的浮动源线。 选择浮置的源极线使得排列位线和行中的不同存储器单元的源位线之间的距离最大化。 以这种方式，可以减小这些漏极位线和源极线之间的漏电流。

公开(公告)号：US07443732B2

公开(公告)日：2008-10-28

申请号：US11229527

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael A. VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Quang Le

IPC分类号： G11C11/34

CPC分类号： G11C5/147 ,  G11C16/12

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC分类号： G11C17/00

CPC分类号： G11C5/147 ,  G11C16/12

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US07453724B2

公开(公告)日：2008-11-18

申请号：US11931992

申请日：2007-10-31

申请人： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

发明人： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US07307878B1

公开(公告)日：2007-12-11

申请号：US11212850

申请日：2005-08-29

申请人： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

发明人： Aaron Lee ,  Hounien Chen ,  Sachit Chandra ,  Nancy Leong ,  Guowei Wang

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/0475 ,  G11C16/3454 ,  G11C16/3459

摘要： A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器件进行编程的方法，其中每个存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收标识阵列中的多个存储单元的编程窗口。 在编程窗口中从多个存储器单元识别要编程的第一组存储器单元。 第一组存储器单元被编程，并且验证第一组存储器单元的编程状态。

公开(公告)号：US20090273998A1

公开(公告)日：2009-11-05

申请号：US12114966

申请日：2008-05-05

申请人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

发明人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC分类号： G11C7/06

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

摘要翻译： 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。

公开(公告)号：US20080130371A1

公开(公告)日：2008-06-05

申请号：US11950811

申请日：2007-12-05

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/12 ,  G11C16/28

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710). For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200). For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07804715B2

公开(公告)日：2010-09-28

申请号：US12114966

申请日：2008-05-05

申请人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

发明人： Hongtau Mu ,  Nian Yang ,  Fan Wan Lai ,  Guowei Wang

IPC分类号： G11C16/06

CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C7/08 ,  G11C2207/063

摘要： A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.

摘要翻译： 存储器件包括用于感测位单元的状态的读出放大器。 读出放大器包括通过开关连接的两个输入端。 一个输入端子连接到一个节点，由此通过该节点的电流表示由位单元和参考电流所画出的电流差。 在第一阶段期间，读出放大器的输入端之间的开关闭合，使得两个输入端施加公共电压。 在第二阶段期间，开关被打开，并且感测放大器基于通过节点的电流来感测存储在位单元的信息的状态。 通过使用开关来连接和断开两相中的读出放大器的输入，可以确定存储在位单元中的信息的状态的精度和速度。