公开(公告)号：US06693818B2

公开(公告)日：2004-02-17

申请号：US10376848

申请日：2003-02-28

Applicant: Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

Inventor： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC: G11C506

CPC classification number: G11C7/1021 ,  G11C8/10

Abstract: A semiconductor integrated circuit includes first to eighth column selection transistors and ninth to twelfth column selection transistors. The ninth column selection transistor is connected to the first and second column selection transistors. The tenth column selection transistor is connected to the third and fourth column selection transistors. The eleventh column selection transistor is connected to the fifth and sixth column selection transistors. The twelfth column selection transistor is connected to the seventh and eighth column selection transistors. A first column selection line is connected to gates of the first, third, fifth and seventh column selection transistors. A second column selection line is connected to gates of the second, fourth, sixth and eighth column selection transistors. Third to sixth column selection lines are connected to gates of the ninth to twelfth column selection transistors, respectively.

Abstract translation: 半导体集成电路包括第一至第八列选择晶体管和第九至第十十列选择晶体管。 第九列选择晶体管连接到第一和第二列选择晶体管。 第十列选择晶体管连接到第三和第四列选择晶体管。 第十列选择晶体管连接到第五和第六列选择晶体管。 第十二列选择晶体管连接到第七和第八列选择晶体管。 第一列选择线连接到第一，第三，第五和第七列选择晶体管的栅极。 第二列选择线连接到第二，第四，第六和第八列选择晶体管的栅极。 第三至第六列选择线分别连接到第九至第十二列选择晶体管的栅极。

公开(公告)号：US06226224B1

公开(公告)日：2001-05-01

申请号：US09502016

申请日：2000-02-11

Applicant: Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

Inventor： Hironori Banba ,  Hitoshi Shiga ,  Shigeru Atsumi ,  Akira Umezawa

IPC: G11C700

CPC classification number: G11C5/143 ,  G11C5/145 ,  G11C5/147 ,  G11C16/30

Abstract: A semiconductor integrated circuit device according to the present invention includes a booster circuit 1 for raising an external power supply voltage Vccext, a level detecting circuit 2 for detecting fluctuation in a stepped-up voltage Vccint2, an internal voltage generating circuit 3 for generating an internal voltage Vccint on the basis of the stepped-up voltage Vccint2, an address buffer 4, an address decoder 5, and a memory cell array 6 of an EEPROM structure. The level detecting circuit 2 includes a first level detecting part for performing level detection during a memory access state, and a second level detecting part for performing level detection during a stand-by state. During the stand-by state, the internal voltage generating circuit 3 short-circuits the stepped-up voltage Vccint2 and the internal voltage Vccint. The second level detecting part has lower power consumption than that of the first level detecting part, so that it is possible to reducing the power consumption during the stand-by state without lowering the driving voltage.

Abstract translation: 根据本发明的半导体集成电路器件包括用于提高外部电源电压Vccext的升压电路1，用于检测升压电压Vccint2中的波动的电平检测电路2，用于产生内部电压的内部电压产生电路3 基于升压电压Vccint2的电压Vccint，地址缓冲器4，地址解码器5和EEPROM结构的存储单元阵列6。 电平检测电路2包括用于在存储器访问状态期间执行电平检测的第一电平检测部分和用于在待机状态期间执行电平检测的第二电平检测部分。 在待机状态下，内部电压产生电路3使升压电压Vccint2和内部电压Vccint短路。 第二电平检测部件具有比第一电平检测部件低的功率消耗，从而可以在不降低驱动电压的情况下降低待机状态下的功耗。

公开(公告)号：US08902662B2

公开(公告)日：2014-12-02

申请号：US13226180

申请日：2011-09-06

Applicant: Hitoshi Shiga ,  Masahiro Yoshihara

Inventor： Hitoshi Shiga ,  Masahiro Yoshihara

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: According to one embodiment, a memory system includes a first nonvolatile semiconductor memory, a second nonvolatile semiconductor memory and a controller. The first memory has memory cells and executes a first operation that is at least one of write, read, and erase operations with respect to the memory cells. The first operation includes a first sub-operation and a second-sub operation that consume a current which is equal to or higher than a predetermined current. The second memory has memory cells and executes a second operation that is at least one of write, read, and erase operations with respect to the memory cells. The second operation includes a third sub-operation and a fourth sub-operation that consume a current which is equal to or higher than the predetermined current. The controller controls the first operation and the second operation of the first memory and the second memory.

Abstract translation: 根据一个实施例，存储器系统包括第一非易失性半导体存储器，第二非易失性半导体存储器和控制器。 第一存储器具有存储器单元并且执行与存储器单元相关的写入，读取和擦除操作中的至少一个的第一操作。 第一操作包括消耗等于或高于预定电流的电流的第一子操作和第二子操作。 第二存储器具有存储单元并且执行与存储单元相关的写入，读取和擦除操作中的至少一个的第二操作。 第二操作包括消耗等于或高于预定电流的电流的第三子操作和第四子操作。 控制器控制第一存储器和第二存储器的第一操作和第二操作。

公开(公告)号：US08432737B2

公开(公告)日：2013-04-30

申请号：US13217512

申请日：2011-08-25

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34

CPC classification number: G11C29/025 ,  G11C16/26 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: When performing a word line leak test to determine a leak state of the word lines, the control circuit applies, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data. Thereafter, it switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state. After a lapse of a certain time from switching of the transfer transistors to a nonconductive state, it activates the sense amplifier circuit to perform a read operation in the memory cell array. Then it compares a result of the read operation with an expectation value corresponding to the test pattern data.

Abstract translation: 当进行字线泄漏测试以确定字线的泄漏状态时，控制电路从电压控制电路向连接到用测试图形数据写入的存储单元阵列的字线施加与测试图案数据相对应的电压 。 此后，它将传输晶体管切换到非导通状态，从而将字线设置为浮置状态。 在从转换晶体管切换到非导通状态经过一段时间之后，它激活读出放大器电路，以在存储单元阵列中执行读取操作。 然后将读取操作的结果与对应于测试图案数据的期望值进行比较。

公开(公告)号：US08036034B2

公开(公告)日：2011-10-11

申请号：US12564425

申请日：2009-09-22

Applicant: Hitoshi Shiga ,  Yoshihisa Kondo

Inventor： Hitoshi Shiga ,  Yoshihisa Kondo

IPC: G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/00

Abstract: A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.

Abstract translation: 半导体存储装置包括：读出放大器电路; 第一数据保持电路和第二数据保持电路，被配置为保持数据和阈值电压信息，第二数据保持电路将数据和阈值电压信息输出到外部; 以及控制电路，被配置为控制操作。 感测放大器电路被配置为同时执行数据读取操作和阈值电压信息读取操作。 控制电路被配置为控制读取操作，使得先前完成读取操作的数据或阈值电压信息中的任何一个从第二数据保持电路输出，另一个数据或阈值电压信息 读取操作尚未完成，从存储单元阵列中读出并保留在第一数据保持电路中。

公开(公告)号：US07839678B2

公开(公告)日：2010-11-23

申请号：US12560503

申请日：2009-09-16

Applicant: Hitoshi Shiga

Inventor： Hitoshi Shiga

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5641

Abstract: A NAND type flash memory includes first to third memory cell transistors having current paths connected in series between one end of a current path of each of first and second selection transistors, and each having a control gate and a charge storage layer, the first and second memory cell transistors being adjacent to the first and second selection transistors, the third memory cell transistor being positioned between the first and second memory cell transistors, the third memory cell transistor holding data having not less than three bits, the first memory cell transistor holding 2-bit data in which middle and upper pages is written by skipping a lower page, and a lower page verify voltage being set when writing the middle page, and a middle page verify voltage is set when writing the upper page, changing a position of a threshold distribution of the first memory cell transistor.

Abstract translation: NAND型闪存包括第一至第三存储单元晶体管，其具有串联连接在第一和第二选择晶体管中的每一个的电流路径的一端之间的电流路径，并且每个存储单元晶体管具有控制栅极和电荷存储层，第一和第二 存储单元晶体管与第一和第二选择晶体管相邻，第三存储单元晶体管位于第一和第二存储单元晶体管之间，第三存储单元晶体管保持具有不少于3位的数据，第一存储单元晶体管保持2 通过跳过下页来写入中间页和上页的位数数据，以及写入中间页时设置的下页验证电压，并且在写入上页时设置中间页验证电压，改变位置 第一存储单元晶体管的阈值分布。

公开(公告)号：US20100208519A1

公开(公告)日：2010-08-19

申请号：US12706306

申请日：2010-02-16

Applicant: Hitoshi SHIGA ,  Osamu Nagao

Inventor： Hitoshi SHIGA ,  Osamu Nagao

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/3404

Abstract: First and second data retaining circuits retain data read from memory cell and threshold voltage information indicating where in one of plural threshold voltage distributions threshold voltage of memory cell is located. Calculation device executes calculations among data retained in first and second data retaining circuit and data read by sense amplifier.Control circuit executes first operation of reading data from adjoining memory cell connected to second word line adjoining first word line connected to selected memory cell and retaining the data in first data retaining circuit, and second operation of changing respective word line voltages applied to first word line for reading data or threshold voltage information among plural values and selecting one of plural data read out by the plural values based on data retained in first data retaining circuit. Third operation of externally outputting selected data is executed simultaneously with one of successive first and second operations.

Abstract translation: 第一和第二数据保持电路保持从存储单元读取的数据和指示存储单元的多个阈值电压分布阈值电压位于何处的阈值电压信息。 计算装置执行在第一和第二数据保持电路中保留的数据和由读出放大器读取的数据之间的计算。 控制电路执行从连接到与选择的存储单元连接的第一字线相邻的第二字线的相邻存储单元读取数据并将数据保存在第一数据保持电路中的第一操作，以及改变施加到第一字线的各字线电压的第二操作 用于在多个值之间读取数据或阈值电压信息，并且基于保留在第一数据保持电路中的数据选择由多个值读出的多个数据中的一个。 在连续的第一和第二操作之一中同时执行外部输出所选数据的第三操作。

公开(公告)号：US20100149867A1

公开(公告)日：2010-06-17

申请号：US12552671

申请日：2009-09-02

Applicant: Hiroaki Tanaka ,  Hitoshi Shiga

Inventor： Hiroaki Tanaka ,  Hitoshi Shiga

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory which includes a block having a plurality of memory cell groups, each of the memory cell groups being electrically connected to a plurality of bit lines and electrically connected to a common word line, each memory cell being recordable of a plurality of bits, a first register which stores information obtained by correcting first data to be written to a first word line, and a control circuit which sets a set potential in the first register and writes the bits to a write target first memory cell at a time using the information in the first register, the set potential being obtained by subtracting, from a target potential to be finally set in the first memory cell, a potential increase which is generated by setting a potential in an unwritten second memory cell adjacent to the first memory cell.

Abstract translation: 非易失性半导体存储器件包括非易失性存储器，其包括具有多个存储单元组的块，每个存储单元组电连接到多个位线并电连接到公共字线，每个存储器单元可记录 多个比特的第一寄存器，存储通过校正要写入第一字线的第一数据而获得的信息的第一寄存器，以及设置第一寄存器中的置位电位并将该位写入写入目标第一存储单元的控制电路 在使用第一寄存器中的信息的同时，通过从第一存储器单元中最终设置的目标电位减去通过将未写入的第二存储单元中的电位设置为相邻而产生的电位增加而获得的设定电位 到第一个存储单元。

公开(公告)号：US07729178B2

公开(公告)日：2010-06-01

申请号：US11849891

申请日：2007-09-04

Applicant: Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

Inventor： Yasushi Kameda ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC: G11C7/10

CPC classification number: G11C16/102

Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07372744B2

公开(公告)日：2008-05-13

申请号：US11216215

申请日：2005-09-01

Applicant: Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

Inventor： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC: G11C7/10

CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

Abstract translation: 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。