公开(公告)号：US08208306B2

公开(公告)日：2012-06-26

申请号：US13154891

申请日：2011-06-07

Applicant: Hong-Beom Pyeon ,  Jin-ki Kim

Inventor： Hong-Beom Pyeon ,  Jin-ki Kim

IPC: G11C11/34

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

Abstract: Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.

Abstract translation: 通用NAND闪存单元块中的每个存储单元串连接到公共源线（CLS）。 集中生成用于应用于CSL的值并将其分配给对应于每个NAND闪存单元块的本地开关逻辑单元。 对于源行页面编程，分发线可以称为全局公用源线（GCSL）。 在NAND闪存单元块的阵列中，一次仅选择一个NAND闪存单元块进行编程。 为了降低功耗，只有选定的NAND闪存单元块才接收到指示GCSL上的值的CSL上的值。 此外，未选择的NAND闪存单元块的CSL可以通过主动连接到地来禁用。

公开(公告)号：US08194481B2

公开(公告)日：2012-06-05

申请号：US12640388

申请日：2009-12-17

Applicant: Hong-Beom Pyeon

Inventor： Hong-Beom Pyeon

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C11/412 ,  G11C7/20 ,  G11C8/10 ,  G11C8/16 ,  G11C11/413 ,  G11C11/417

Abstract: A semiconductor device that can implement a method comprising selecting a group of rows of auxiliary cells forming part of an auxiliary memory unit, the auxiliary cells being arranged into rows and columns; driving a plurality of bitlines each connected to a respective column of the auxiliary cells, so as to set each of the auxiliary cells to a first logic state; writing input data to selected ones of a plurality of main cells, wherein each of the auxiliary cells corresponds to a respective set of the main cells; selecting a particular row of auxiliary cells that includes at least one auxiliary cell whose corresponding main cells are among the selected cells; and driving the bitlines so as to set the at least one auxiliary cell to a second logic state different from the first logic state.

Abstract translation: 一种半导体器件，其可以实现包括选择构成辅助存储器单元的一部分的辅助单元的一组行的方法，所述辅助单元被布置成行和列; 驱动各个连接到辅助单元的相应列的位线，以便将每个辅助单元设置为第一逻辑状态; 将输入数据写入多个主单元中的选定的主单元，其中每个辅助单元对应于相应的主单元组; 选择包括至少一个辅助单元的特定行的辅助单元，其中相应的主单元位于所选单元中; 并且驱动所述位线以将所述至少一个辅助单元设置为不同于所述第一逻辑状态的第二逻辑状态。

公开(公告)号：US08131913B2

公开(公告)日：2012-03-06

申请号：US12254315

申请日：2008-10-20

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G06F12/02

CPC classification number: G11C5/00 ,  G06F12/06 ,  G06F13/1684 ,  G06F2212/1032 ,  G06F2212/2022 ,  G11C7/22 ,  G11C8/12

Abstract: A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.

Abstract translation: 一种用于将命令选择性地广播到与存储器控制器串联连接的多个设备的子集的方法和系统，其中多个设备中的每一个具有唯一的标识号（ID）。 存储器控制器指定要执行命令的设备的子集，排除未被选择的设备执行命令。 存储器控制器将指定设备的ID号编码为单个编码地址，并将该命令与编码地址一起发送到串联连接的设备。 每个设备以串行比特流接收分组，并使用其ID号对编码的地址进行解码，以便确定是否被选择。 如果选择了设备，则执行该命令。 否则，报文转发，不执行该命令。

公开(公告)号：US08069328B2

公开(公告)日：2011-11-29

申请号：US11606407

申请日：2006-11-29

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G06F12/00

CPC classification number: G11C7/20 ,  G11C16/20

Abstract: Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

Abstract translation: 方法和系统提供了菊花链级联配置中的设备的识别。 设备上的输入电路在器件的上电，复位或其他操作之后接收指示器件配置的输入信号。 脉冲发生器响应于该操作产生脉冲，当输入信号指示器件配置时发生脉冲。 状态锁存寄存器响应于所接收的脉冲存储输入信号的状态，由此存储指示各个器件的配置的状态。 在该操作之后，输入电路可以接收与设备配置无关的信号，从而避免需要额外的引脚分配。

公开(公告)号：US08064260B2

公开(公告)日：2011-11-22

申请号：US12903271

申请日：2010-10-13

Applicant: Hong Beom Pyeon ,  Jin-Ki Kim

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C16/04

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C5/147 ,  H02M3/073

Abstract: Power supplies in flash memory devices are disclosed. A first section of a flash memory device includes non-volatile memory for storing data. A second section of the flash memory device includes at least first and second pumping circuits. The first pumping circuit receives a first voltage and produces, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level. The second pumping circuit has an input coupled to the first pumping circuit output for cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage to produce a third voltage at a third voltage level that is higher than the second voltage level.

Abstract translation: 公开了闪存设备中的电源。 闪存器件的第一部分包括用于存储数据的非易失性存储器。 闪存器件的第二部分至少包括第一和第二泵浦电路。 第一泵送电路接收第一电压，并且在第一泵送电路的输出处产生高于第一电压电平的第二电压电平的第二电压。 第二泵浦电路具有耦合到第一泵浦电路输出的输入端，用于协同地采用第一泵浦电路从大于第一电压的电压泵浦，以产生高于第二电压电平的第三电压电平的第三电压 。

公开(公告)号：US08000144B2

公开(公告)日：2011-08-16

申请号：US12732745

申请日：2010-03-26

Applicant: Jin-Ki Kim ,  Hong Beom Pyeon

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C8/00

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US20110194351A1

公开(公告)日：2011-08-11

申请号：US13091479

申请日：2011-04-21

Applicant: Jin-Ki KIM ,  Hong Beom PYEON

Inventor： Jin-Ki KIM ,  Hong Beom PYEON

IPC: G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

Abstract translation: 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

公开(公告)号：US20110163423A1

公开(公告)日：2011-07-07

申请号：US13046197

申请日：2011-03-11

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: H01L23/538 ,  H01L21/60

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/066 ,  G11C16/06 ,  G11C19/00 ,  H01L21/76898 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00

Abstract: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.

Abstract translation: 提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。 多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接 至少两块芯片。 公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。 输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。 堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。 当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

公开(公告)号：US20110131445A1

公开(公告)日：2011-06-02

申请号：US13022166

申请日：2011-02-07

Applicant: Hong Beom PYEON ,  Jin-Ki KIM ,  HakJune OH

Inventor： Hong Beom PYEON ,  Jin-Ki KIM ,  HakJune OH

IPC: G06F11/00

CPC classification number: G06F13/4243 ,  G06F13/4247

Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Abstract translation: 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US20110087823A9

公开(公告)日：2011-04-14

申请号：US11622828

申请日：2007-01-12

Applicant: Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM

IPC: G06F13/00 ,  G06F12/02

CPC classification number: G06F13/4243 ,  G06F12/0676

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM和NAND-，NOR-，AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 串行输入中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连配置的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。