公开(公告)号：US20150270211A1

公开(公告)日：2015-09-24

申请号：US14220814

申请日：2014-03-20

Applicant: Mauro Kobrinsky ,  Tatyania Andryushchenko ,  Ramanan Chebiam ,  Hui Jae Yoo

Inventor： Mauro Kobrinsky ,  Tatyania Andryushchenko ,  Ramanan Chebiam ,  Hui Jae Yoo

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

Abstract translation: 互连结构，包括设置在下层互连特征的顶表面上的选择通孔，以及选择性地形成这种柱的制造技术。 以下实施例中，可以独立于通孔开口中的配准误差来维持最小互连线间距。 在实施例中，选择性通孔支柱的底部横向尺寸小于通孔开口的底部横向尺寸，在该通孔开口内设置有支柱。 导电通孔的形成可优先于由通孔开口暴露的下互连特征的顶表面。 随后沉积的电介质材料回填了超过互连特征的通孔开口的部分，其中没有形成导电通孔。 上级互连功能着陆在选择性通孔上以与较低级别特征电互连。

公开(公告)号：US20130292835A1

公开(公告)日：2013-11-07

申请号：US13976835

申请日：2011-12-20

Applicant: Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Abstract translation: 适合于3D地形的电介质扩散屏障的保形密封电介质膜。 在实施例中，电介质扩散阻挡层包括介电层，例如金属氧化物，其可以通过原子层沉积（ALD）技术沉积，其共形度和密度大于常规的基于二氧化硅的膜沉积的二氧化硅基膜 用于较薄连续密封扩散屏障的PECVD工艺。 在另外的实施例中，扩散阻挡层是包括高k电介质层和低k或中间介电层（例如双层）的多层膜，以降低扩散阻挡层的介电常数。 在其它实施方案中，形成高k电介质层（例如金属硅酸盐）的硅酸盐，以通过调节硅酸盐的硅含量来降低扩散阻挡层的k值，同时保持高的膜保形性和密度。

公开(公告)号：US08039920B1

公开(公告)日：2011-10-18

申请号：US12948410

申请日：2010-11-17

Applicant: Sean W. King ,  Hui Jae Yoo

Inventor： Sean W. King ,  Hui Jae Yoo

IPC: H01L21/00

CPC classification number: H02J7/0045 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76883

Abstract: Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.

Abstract translation: 描述了形成微电子结构的方法和相关结构。 这些方法可以包括在布置在基板上的层间电介质材料中的互连开口中形成导电材料，在电介质层的表面和导电材料的表面上形成低密度电介质材料，并形成高 密度介电阻挡层在低密度电介质层上。

公开(公告)号：US20230093064A1

公开(公告)日：2023-03-23

申请号：US17477850

申请日：2021-09-17

Applicant: Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo

IPC: H01L29/786

Abstract: Integrated circuit (IC) devices implementing pairs of thin-film transistors (TFTs) with shared contacts, and associated systems and methods, are disclosed. An example IC device may include a support structure, a channel layer provided over the support structure, where the channel layer includes a thin-film semiconductor material, a first TFT with a channel region that includes a first portion of the channel layer, and a second TFT with a channel region that includes a second portion of the channel layer. In some embodiments, a source or a drain (S/D) contact of the first TFT may be a shared contact that is also a S/D contact of the second TFT. In other embodiments, a gate contact/stack of the first TFT may be a shared contact/stack that is also a gate contact/stack of the second TFT.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20140029181A1

公开(公告)日：2014-01-30

申请号：US13560930

申请日：2012-07-27

Applicant: Florian Gstrein ,  Hui Jae Yoo ,  Jacob M. Faber ,  James S. Clarke

Inventor： Florian Gstrein ,  Hui Jae Yoo ,  Jacob M. Faber ,  James S. Clarke

IPC: H01L23/522 ,  G06F1/16 ,  H01L21/768

CPC classification number: H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards interlayer interconnects and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, one or more device layers disposed on the semiconductor substrate, and one or more interconnect layers disposed on the one or more device layers, the one or more interconnect layers including interconnect structures configured to route electrical signals to or from the one or more device layers, the interconnect structures comprising copper (Cu) and germanium (Ge). Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及层间互连和相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的一个或多个器件层，以及设置在该一个或多个器件层上的一个或多个互连层，所述一个或多个互连层包括被配置为布线 信号到或来自一个或多个器件层，包括铜（Cu）和锗（Ge）的互连结构。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20130260553A1

公开(公告)日：2013-10-03

申请号：US13893143

申请日：2013-05-13

Applicant: Hui Jae Yoo ,  Jeffrey D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

Inventor： Hui Jae Yoo ,  Jeffrey D. Bielefeld ,  Sean W. King ,  Sridhar Balakrishnan

IPC: H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/2855 ,  H01L21/32053 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Abstract translation: 在后端金属化的层间电介质层（ILD）中形成绝缘线的工艺包括在使阻挡前体中的至少一个合金元素引起的金属屏障前体之间形成电介质势垒 ILD。 因此，介电阻挡层是自形成的自对准势垒。 热处理在使至少一种合金元素从其较高浓度的区域迁移到其较低浓度的区域的条件下进行以进一步形成电介质阻挡层。 通过该方法制造各种装置。