公开(公告)号：US20100060616A1

公开(公告)日：2010-03-11

申请号：US12461895

申请日：2009-08-27

Applicant: Hyun Jin Shin ,  Seung Jung Lee

Inventor： Hyun Jin Shin ,  Seung Jung Lee

IPC: G06F3/038

CPC classification number: G09G3/20 ,  G09G2300/0426 ,  G09G2310/027

Abstract: A data line driver having a double column architecture includes a first driver cell including a first decoder, the first driver cell being connected to a first data line, and a second driver cell including a second decoder adjacent to the first decoder, the second driver cell being connected to a second data line.

Abstract translation: 具有双列架构的数据线驱动器包括：第一驱动器单元，包括第一解码器，第一驱动器单元连接到第一数据线;以及第二驱动器单元，其包括与第一解码器相邻的第二解码器，第二驱动器单元 连接到第二数据线。

公开(公告)号：US20160343729A1

公开(公告)日：2016-11-24

申请号：US15142365

申请日：2016-04-29

Applicant: Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

Inventor： Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成结构，所述结构包括金属图案，所述金属图案的至少一部分被暴露; 形成预备的缓冲氧化物层以覆盖该结构，金属氧化物层形成在金属图案的暴露部分; 并且使金属氧化物层脱氧，使得预备缓冲氧化物层转变成缓冲氧化物层。

公开(公告)号：US20070010068A1

公开(公告)日：2007-01-11

申请号：US11481928

申请日：2006-07-07

Applicant: Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

Inventor： Yong-Sun Lee ,  Jai-Dong Lee ,  Bong-Hyun Kim ,  Man-Sug Kang ,  Jung-Hwan Kim ,  Hyun-Jin Shin ,  Won-Seok Yoo ,  Seung-Mok Shin

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/32105 ,  H01L21/28273 ,  H01L29/42324

Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Abstract translation: 本发明的示例性实施例涉及制造半导体器件的方法。 本发明的其它示例实施例涉及制造具有栅电极的半导体器件的方法。 在制造半导体器件的方法中，可以在半导体衬底上形成栅电极。 可以通过自由基再氧化工艺固化或修复半导体衬底和栅电极的侧壁的损伤，以在半导体衬底和栅电极上形成氧化物层。 可以通过在半导体衬底上提供氮气同时将半导体衬底的温度提高到第一温度以在氮气气氛下钝化栅电极的表面来进行自由基再氧化工艺，从而将氧气提供到 半导体衬底，同时将温度从第一温度升至第二温度，以进行第一氧化工艺和/或在第二温度下进行第二氧化工艺。

公开(公告)号：US08691927B2

公开(公告)日：2014-04-08

申请号：US13377466

申请日：2010-06-10

Applicant: Hyun Jin Shin ,  Kyung Seog Youk ,  Han Hong Kim

Inventor： Hyun Jin Shin ,  Kyung Seog Youk ,  Han Hong Kim

IPC: C08F114/06 ,  C08F2/24

CPC classification number: C08F14/06 ,  C08F259/04 ,  C08F2/18 ,  C08F2/22 ,  C08F214/20

Abstract: Provided are a vinyl chloride-based resin formed by polymerization of vinyl chloride-based small seed particles having an average particle diameter range of 0.15 μm to 0.5 μm prepared by emulsion polymerization and vinyl chloride-based large seed particles having an average particle diameter range of 0.51 μm to 0.8 μm prepared by micro-suspension polymerization, in which a content ratio (weight ratio) of the large seed particles to the small seed particles is in a range of 1 to 2, and a method of preparing the vinyl chloride-based resin. Excellent low viscosity characteristics of the vinyl chloride resin at high and low shear rates may be obtained by controlling the particle size of the small seed prepared by emulsion polymerization.

Abstract translation: 本发明提供一种氯乙烯系树脂，其通过聚合具有通过乳液聚合制备的平均粒径范围为0.15μm至0.5μm的氯乙烯基小种子颗粒和平均粒径范围为氯乙烯的大型种子颗粒 通过微悬浮聚合制备的0.51μm〜0.8μm，其中大种子颗粒与小种子颗粒的含量比（重量比）在1至2的范围内，以及制备氯乙烯基 树脂。 通过控制通过乳液聚合制备的小种子的粒度，可以获得高低剪切速率下氯乙烯树脂的优异的低粘度特性。

公开(公告)号：US20170033044A1

公开(公告)日：2017-02-02

申请号：US15160137

申请日：2016-05-20

Applicant: Ji-Hoon CHOI ,  Jung Ho KIM ,  Dongkyum KIM ,  Seulye KIM ,  Jintae NOH ,  Hyun-Jin SHIN ,  SeungHyun LIM

Inventor： Ji-Hoon CHOI ,  Jung Ho KIM ,  Dongkyum KIM ,  Seulye KIM ,  Jintae NOH ,  Hyun-Jin SHIN ,  SeungHyun LIM

IPC: H01L23/522 ,  G11C8/10 ,  H01L23/532 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.

Abstract translation: 提供半导体器件。 半导体器件包括堆叠结构，其包括交替堆叠在衬底上的绝缘图案和电极结构以及垂直穿过堆叠结构的垂直沟道结构。 每个电极结构包括具有第一侧壁和与第一侧壁相对的第二侧壁的导电图案，第一侧壁上的第一蚀刻防止图案和第二侧壁上的第二蚀刻防止图案。