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    SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES HAVING A CONTROL GATE ELECTRODE INCLUDING A METAL LAYER FILLING A GAP BETWEEN ADJACENT FLOATING GATES AND METHODS OF FABRICATING THE SAME 审中-公开
    具有控制栅极电极的半导体器件，包括在相邻浮动栅之间填充间隙的金属层及其制造方法

    公开(公告)号：US20120104482A1

    公开(公告)日：2012-05-03

    申请号：US13241387

    申请日：2011-09-23

    申请人： Hong-Suk KIM ,  Jun Kyu AHN ,  Jae Young AHN ,  Ki Hyun HWANG ,  Yong Hyun KWON

    发明人： Hong-Suk KIM ,  Jun Kyu AHN ,  Jae Young AHN ,  Ki Hyun HWANG ,  Yong Hyun KWON

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L29/40114

    摘要： A semiconductor device includes a device isolation layer defining a plurality of active regions of a semiconductor substrate, floating gates and a control gate electrode in which the lowermost part of the electrode is constituted by a metal layer. The control gate electrode crosses over the active regions. The floating gates are disposed between the control gate electrode and the active regions. The tops of the floating gates are disposed at a level above the level of the top of the device isolation layer such that a gap is defined between adjacent ones of the floating gates. A region of the gap is filled with the metal layer of the control gate electrode.

    摘要翻译： 半导体器件包括限定半导体衬底的多个有源区的器件隔离层，浮置栅极和控制栅电极，其中电极的最下部分由金属层构成。 控制栅电极跨越有源区。 浮置栅极设置在控制栅电极和有源区之间。 浮置栅极的顶部设置在高于器件隔离层的顶部的高度的水平面上，使得在相邻的浮动栅极之间限定间隙。 间隙的区域被控制栅电极的金属层填充。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180122822A1

    公开(公告)日：2018-05-03

    申请号：US15610923

    申请日：2017-06-01

    申请人： Joon-Suk LEE ,  Hong-Suk KIM ,  Jae-Young AHN ,  Han-Jin LIM

    发明人： Joon-Suk LEE ,  Hong-Suk KIM ,  Jae-Young AHN ,  Han-Jin LIM

    IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/10

    CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1045 ,  H01L29/66666 ,  H01L29/7827

    摘要： A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.