公开(公告)号：US06579552B1

公开(公告)日：2003-06-17

申请号：US09661102

申请日：2000-09-13

Applicant: Roger R. Myhre ,  Lawrence K. Cooper ,  Jeffrey K. Cooper ,  Daniel L. Peterson ,  James A. Cooper

Inventor： Roger R. Myhre ,  Lawrence K. Cooper ,  Jeffrey K. Cooper ,  Daniel L. Peterson ,  James A. Cooper

IPC: A01F1500

CPC classification number: A01F15/00 ,  A01F15/005 ,  Y10T83/0505

Abstract: The present invention relates to a method for forming a compressed and cut bale of fibrous material, whereby the bale of fibrous material has at least one cut that allows the material to be separated into two distinct and separate layers. The present invention also relates to the compressed and cut fibrous material.

Abstract translation: 本发明涉及一种用于形成压缩和切割的纤维材料包的方法，由此纤维材料束具有至少一个允许将材料分离成两个不同且分离的层的切口。 本发明还涉及压缩和切割的纤维材料。

公开(公告)号：US5465249A

公开(公告)日：1995-11-07

申请号：US798219

申请日：1991-11-26

Applicant: James A. Cooper, Jr. ,  John W. Palmour ,  Calvin H. Carter, Jr.

Inventor： James A. Cooper, Jr. ,  John W. Palmour ,  Calvin H. Carter, Jr.

IPC: G11C14/00 ,  G11C11/404 ,  G11C17/00 ,  H01L21/8229 ,  H01L21/8246 ,  H01L27/102 ,  H01L27/105 ,  H01L29/24 ,  G11C11/401

CPC classification number: H01L29/1608 ,  G11C11/404 ,  H01L27/1023

Abstract: A random access memory (RAM) cell in 6H-SiC having storage times when all bias is removed long enough to be considered nonvolatile. The nonvolatile random access memory (NVRAM) cell comprises a bit line, a charge storage device in silicon carbide, and a transistor in silicon carbide connecting the charge storage device to the bit line. The bipolar NVRAM cell has a bipolar transistor with a base region, an emitter region, and a floating collector region, wherein the charge storage device in the bipolar NVRAM is a p-n junction adjacent the floating collector region of the cell. The metal-oxide-semiconductor (MOS) NVRAM has a MOS field effect transistor (MOSFET) with a channel region, a source region, and a drain region, wherein the charge storage device in the MOS NVRAM is a MOS capacitor adjacent the drain region of the MOSFET.

Abstract translation: 6H-SiC中的随机存取存储器（RAM）单元具有所有偏移被去除的存储时间，足以被认为是非易失性的。 非易失性随机存取存储器（NVRAM）单元包括位线，碳化硅中的电荷存储装置和将电荷存储装置连接到位线的碳化硅晶体管。 双极NVRAM单元具有双极晶体管，其具有基极区域，发射极区域和浮动集电极区域，其中双极NVRAM中的电荷存储器件是邻近电池的浮置集电极区域的p-n结。 金属氧化物半导体（MOS）NVRAM具有沟道区，源极区和漏极区的MOS场效应晶体管（MOSFET），其中MOS NVRAM中的电荷存储装置是与漏极区相邻的MOS电容 的MOSFET。

公开(公告)号：US4894689A

公开(公告)日：1990-01-16

申请号：US687127

申请日：1984-12-28

Applicant: James A. Cooper, Jr. ,  Karvel K. Thornber

Inventor： James A. Cooper, Jr. ,  Karvel K. Thornber

IPC: H01L29/78 ,  H01L47/00 ,  H01L47/02

CPC classification number: H01L47/02

Abstract: A transferred electron device is described in which the charge of the drifting packets is imaged perpendicular to the charge-packet direction so that essentially all of the packet-averaged, space-charge field is normal to the drift direction. This permits continuous formation of contiguous charge packets.

Abstract translation: 描述了转移的电子器件，其中漂移包的电荷垂直于电荷包方向成像，使得基本上所有的分组平均的空间电荷场垂直于漂移方向。 这允许连续形成连续的电荷包。

公开(公告)号：US4719496A

公开(公告)日：1988-01-12

申请号：US631041

申请日：1986-02-12

Applicant: Federico Capasso ,  James A. Cooper, Jr. ,  Karvel K. Thornber

Inventor： Federico Capasso ,  James A. Cooper, Jr. ,  Karvel K. Thornber

IPC: H01L29/10 ,  H01L29/15 ,  H01L29/36 ,  H01L29/861 ,  H01L45/00 ,  H01L29/205

CPC classification number: H01L29/157 ,  H01L29/1029 ,  H01L29/155 ,  H01L29/365 ,  H01L29/8618

Abstract: Semiconductor structures suitable for repeated velocity overshoot are described. The structure comprises at least two velocity overshoot sections with each section comprising a first semiconductor region having a rapid change in potential and a dimension such that the carrier transit time is comparable to or shorter than the mean scattering time and a second semiconductor region having a more gradual change in potential and a dimension such that the carrier transit time is sufficient to allow the energy relaxation time to be exceeded.

Abstract translation: 描述适用于重复速度超调的半导体结构。 该结构包括至少两个速度过冲部分，每个部分包括具有快速变化的电位的第一半导体区域和使得载流子渡越时间与平均散射时间相当或更短的尺寸，以及具有更多的第二半导体区域 电势的逐渐变化和使得载流子传播时间足以允许超过能量松弛时间的尺寸。

公开(公告)号：US10208648B1

公开(公告)日：2019-02-19

申请号：US15436233

申请日：2017-02-17

Applicant: James A. Cooper

Inventor： James A. Cooper

IPC: F01P11/06 ,  F02M26/30 ,  F01M5/00 ,  F01P3/20 ,  F01P7/14

Abstract: An engine oil cooler backflush valve assembly is provided as a replacement cap to an engine oil cooler EGR coolant supply cover. The backflush valve assembly includes a main body through which a valve stem is inserted. The valve stem has a bushing threadedly attached thereto which moves the valve stem between first and second positions. A removable cap is provided to cover the backflush valve assembly during normal operation and to be removed during backflush operation. A removable lock can also be used to secure the cap and/or bushing to the main body of the assembly.

公开(公告)号：US09065264B2

公开(公告)日：2015-06-23

申请号：US13980011

申请日：2012-01-17

Applicant: James A. Cooper ,  Hon Man Kuan

Inventor： James A. Cooper ,  Hon Man Kuan

IPC: H02G3/16 ,  H02G1/00 ,  H02G3/14 ,  H02G3/18

CPC classification number: H02G3/16 ,  F21V21/03 ,  H02G1/00 ,  H02G3/14 ,  H02G3/18 ,  H02G3/20 ,  Y10T29/49208

Abstract: The invention provides a mount for installing an electrical fixture to an electrical junction box. The mount includes a support configured for independent attachment to said junction box and said electrical fixture respectively for mounting said fixture to said junction box. The mount further includes at least one electrical quick connect member engaged to said support comprising a first connection element for forming an electrical connection with a electrical wire and a second connection element for forming an electrical connection a fixture electrical wires. The first and second connection elements are electrically connected or connectible together to form an electrical connection between the source wires and the fixture wires.

Abstract translation: 本发明提供了一种用于将电气安装件安装到电接线盒的安装座。 安装座包括支撑件，其构造成用于独立地附接到所述接线盒和所述电气固定件，用于将所述固定件安装到所述接线盒。 该安装件还包括与所述支撑件接合的至少一个电快速连接构件，其包括用于与电线形成电连接的第一连接元件和用于形成固定电线的电连接的第二连接元件。 第一和第二连接元件电连接或连接在一起以在源极线和夹具线之间形成电连接。

公开(公告)号：US08133789B1

公开(公告)日：2012-03-13

申请号：US12463054

申请日：2009-05-08

Applicant: James A. Cooper ,  Maherin Matin

Inventor： James A. Cooper ,  Maherin Matin

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

Abstract: A silicon carbide power MOSFET having a drain region of a first conductivity type, a base region of a second conductivity type above the drain region, and a source region of the first conductivity type adjacent an upper surface of the base region, the base region including a channel extending from the source region through the base region adjacent a gate interface surface thereof, the channel having a length less than approximately 0.6 μm, and the base region having a doping concentration of the second conductivity type sufficiently high that the potential barrier at the source end of the channel is not lowered by the voltage applied to the drain. The MOSFET includes self-aligned base and source regions as well as self-aligned ohmic contacts to the base and source regions.

Abstract translation: 具有第一导电类型的漏极区域，位于漏极区域之上的第二导电类型的基极区域和与该基极区域的上表面相邻的第一导电类型的源极区域的碳化硅功率MOSFET，所述基极区域包括 从源极区域延伸通过与其栅极界面表面相邻的基极区域的沟道，沟道具有小于约0.6μm的长度，并且具有足够高的第二导电类型的掺杂浓度的基极区域使得在 通道的源极端不被施加到漏极的电压降低。 MOSFET包括自对准的基极和源极区域以及到基极和源极区域的自对准欧姆接触。

公开(公告)号：US06900133B2

公开(公告)日：2005-05-31

申请号：US10247467

申请日：2002-09-18

Applicant: Jeffrey D. Chinn ,  Michael B. Rattner ,  James A. Cooper ,  Rolf A. Guenther

Inventor： Jeffrey D. Chinn ,  Michael B. Rattner ,  James A. Cooper ,  Rolf A. Guenther

IPC: B81C1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/302

CPC classification number: B81C1/00626 ,  B81B2201/0214 ,  B81B2201/058 ,  B81C99/009 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/3081

Abstract: Disclosed herein is an easy and well-integrated method of etching features to different depths in a crystalline substrate, such as a single-crystal silicon substrate. The method utilizes a specialized masking process and takes advantage of a highly selective etch process. The method provides a system of interconnected, variable depth reservoirs and channels. The plasma used to etch the channels may be designed to provide a sidewall roughness of about 200 nm or less. The resulting structure can be used in various MEMS applications, including biomedical MEMS and MEMS for semiconductor applications.

Abstract translation: 本文公开了一种在晶体衬底（例如单晶硅衬底）中对不同深度蚀刻特征的易于且良好集成的方法。 该方法利用专门的掩蔽过程并利用高选择性蚀刻工艺。 该方法提供了一个互连的，可变深度的储层和通道的系统。 用于蚀刻通道的等离子体可以设计成提供约200nm或更小的侧壁粗糙度。 所得结构可用于各种MEMS应用，包括用于半导体应用的生物医学MEMS和MEMS。

公开(公告)号：US06830950B2

公开(公告)日：2004-12-14

申请号：US10300970

申请日：2002-11-20

Applicant: Jeffrey D. Chinn ,  Rolf A. Guenther ,  Michael B. Rattner ,  James A. Cooper ,  Toi Yue Becky Leung

Inventor： Jeffrey D. Chinn ,  Rolf A. Guenther ,  Michael B. Rattner ,  James A. Cooper ,  Toi Yue Becky Leung

IPC: H01L2100

CPC classification number: B81C1/0096 ,  B81B3/0005 ,  B81C2201/0176 ,  B81C2201/112 ,  B82Y30/00

Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.

Abstract translation: 本文公开了一种改进疏水性自组装单层（SAM）涂层到MEMS结构表面的粘附性的方法，以防止粘结。 该方法包括用包含氧气和任选的氢气的源气体产生的等离子体来预处理MEMS结构的表面。 处理氧化表面，然后与氢气反应以在表面上形成键合的OH基团。 氢源可以作为等离子体源气体的一部分存在，使得在用等离子体处理表面期间产生结合的OH基团。 本文还公开了一种用于MEMS结构的释放和钝化的集成方法。

公开(公告)号：US4841570A

公开(公告)日：1989-06-20

申请号：US48433

申请日：1987-05-11

Applicant: James A. Cooper

Inventor： James A. Cooper

IPC: H04L9/30

CPC classification number: H04L9/3013

Abstract: Method and apparatus are provided for one-way transformation of data according to multiplication and/or exponentiation modulo a prime number. An implementation of the invention permits the one way residue transformation, useful in encryption and similar applications, to be implemented by n-bit computers substantially with no increase in difficulty or complexity over a natural transformation thereby, using a modulus which is a power of two.

Abstract translation: 提供方法和装置，用于根据素数的乘法和/或取幂进行单向数据转换。 本发明的实施方式允许在加密和类似应用中有用的单向残留变换由n位计算机基本上与自然变换相比难以增加难度或复杂度而实现，其中使用的模数为2的幂 。