公开(公告)号：US08347260B2

公开(公告)日：2013-01-01

申请号：US12880228

申请日：2010-09-13

Applicant: Kerry Bernstein ,  James A. Culp ,  Leah M. P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

Inventor： Kerry Bernstein ,  James A. Culp ,  Leah M. P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

IPC: G06F11/22

CPC classification number: G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

Abstract translation: 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

公开(公告)号：US08347259B1

公开(公告)日：2013-01-01

申请号：US13193721

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Critical circuit blocks are identified in a chip design layout, and are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each critical circuit block within each marked region. Each multiplicate layer includes a different type of variant for each identified critical circuit block. The different types of variants correspond to different types of optimization goals to address different issues in circuit performance. Circuit simulation is performed with each type of variants in combination with adjacent circuit blocks as provided in original design. In each marked region, the results of the circuit simulations are evaluated to determine an optimal type among the variants. The optimal type is retained in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant circuit blocks to provide local circuit optimization.

Abstract translation: 关键电路块以芯片设计布局标识，并标记标识区域的标记层。 为每个标记区域内的每个关键电路块生成多重层。 每个多重层包括用于每个识别的关键电路块的不同类型的变体。 不同类型的变体对应于不同类型的优化目标，以解决电路性能中的不同问题。 在原始设计中提供的每种类型的变体与相邻电路块的组合进行电路仿真。 在每个标记区域中，评估电路模拟的结果以确定变体中的最佳类型。 最佳类型保留在每个标记区域中，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体电路块以提供本地电路优化。

公开(公告)号：US20120107969A1

公开(公告)日：2012-05-03

申请号：US12914212

申请日：2010-10-28

Applicant: Stephen E. Fischer ,  James A. Culp ,  Robert T. Sayah

Inventor： Stephen E. Fischer ,  James A. Culp ,  Robert T. Sayah

IPC: H01L21/66 ,  G05B13/04 ,  G06F17/50

CPC classification number: G03F7/705

Abstract: A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions.

Abstract translation: 在为一组数据准备参数和光刻处理条件生成的模拟光刻图案中识别一组光学规则检查器（ORC）标记。 每个ORC标记识别模拟光刻图案中违反ORC规则的特征。 在每个ORC标记中定义一个中心线，并且在每个中心线周围生成最小尺寸区域，其最小宽度符合ORC的规则。 通过从最小尺寸区域去除与ORC标记重叠的区域，在每个ORC标记周围定义故障区域。 添加所有故障区域的区域以定义模拟光刻图案的特征。 可以通过修改数据准备参数和光刻处理条件的集合来评估多个模拟光刻图案或迭代降低的缺点。

公开(公告)号：US20110307846A1

公开(公告)日：2011-12-15

申请号：US13216362

申请日：2011-08-24

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US08042070B2

公开(公告)日：2011-10-18

申请号：US11876853

申请日：2007-10-23

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US20110179391A1

公开(公告)日：2011-07-21

申请号：US12689481

申请日：2010-01-19

Applicant: James A. Culp ,  Lars W. Liebmann

Inventor： James A. Culp ,  Lars W. Liebmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract translation: 本发明提供了一种用于设计用于由基于模型的设计工具（例如OPC或OPC验证）使用的晶圆上目标的方法和计算机程序产品。 通过修改关键尺寸来修改晶圆上目标，以改善或优化电特性，同时还确保满足一个或多个屈服约束。 使用电气优化的目标可以产生更符合设计者意图的经济高效的面罩设计。

公开(公告)号：US07975244B2

公开(公告)日：2011-07-05

申请号：US12019125

申请日：2008-01-24

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Alan E. Rosenbluth

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/44 ,  G03F1/68

Abstract: A method is provided for designing a mask that includes the use of a pixel-based simulation of a lithographic process model, in which test structures are designed for determining numerical and discretization errors associated with the pixel grid as opposed to other model inaccuracies. The test structure has a plurality of rows of the same sequence of features, but each row is offset from other rows along an x-direction by a multiple of a minimum step size, such as used in modifying masks during optical proximity correction. The images for each row are simulated with a lithographic model that uses the selected pixel-grid size and the differences between row images are compared. If the differences between rows exceed or violate a predetermined criterion, the pixel grid size may be modified to minimize discretization and/or numerical errors due to the choice of pixel grid size.

Abstract translation: 提供了一种用于设计包括使用光刻处理模型的基于像素的仿真的掩模的方法，其中测试结构被设计用于确定与像素网格相关的数值和离散化误差，而不是其他模型不准确。 测试结构具有相同序列特征的多行，但是每一行都沿着x方向与其他行偏移最小步长的倍数，例如在光学邻近校正期间用于修改掩模。 使用所选择的像素网格大小的光刻模型来模拟每行的图像，并比较行图像之间的差异。 如果行之间的差异超过或违反预定标准，则可以修改像素网格大小以使由于像素网格大小的选择而导致的离散化和/或数值误差最小化。

公开(公告)号：US07669175B2

公开(公告)日：2010-02-23

申请号：US11747485

申请日：2007-05-11

Applicant: James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

Inventor： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.

Abstract translation: 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。

公开(公告)号：US20090106714A1

公开(公告)日：2009-04-23

申请号：US11876853

申请日：2007-10-23

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F9/45

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

公开(公告)号：US07503028B2

公开(公告)日：2009-03-10

申请号：US11306750

申请日：2006-01-10

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Abstract translation: 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。