公开(公告)号：US20070025156A1

公开(公告)日：2007-02-01

申请号：US11394441

申请日：2006-03-31

申请人： Jun Wan ,  Jeffrey Lutze

发明人： Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10

摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also Teach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

摘要翻译： 调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。 施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，在此之后，定义的最大数量的附加脉冲可以被施加到其它存储器元件，以允许它们也教导相关联的目标阈值电压电平。 该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

公开(公告)号：US07105406B2

公开(公告)日：2006-09-12

申请号：US10600259

申请日：2003-06-20

申请人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

发明人： Jeffrey Lutze ,  Tuan Pham ,  Henry Chien ,  George Matamis

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： Floating gate structures are disclosed that have a projection that extends away from the surface of a substrate. This projection may provide the floating gate with increased surface area for coupling the floating gate and the control gate. In one embodiment, the word line extends downwards on each side of the floating gate to shield adjacent floating gates in the same string. In another embodiment, a process for fabricating floating gates with projections is disclosed. The projection may be formed so that it is self-aligned to the rest of the floating gate.

摘要翻译： 公开了浮动栅极结构，其具有远离衬底的表面延伸的突起。 该突起可以为浮动栅极提供增加的表面积，用于耦合浮动栅极和控制栅极。 在一个实施例中，字线在浮动栅极的每一侧向下延伸以屏蔽相同串中的相邻浮动栅极。 在另一个实施例中，公开了一种用于制造具有突起的浮动栅极的工艺。 突起可以形成为使得其与浮动栅极的其余部分自对准。

公开(公告)号：US20050207222A1

公开(公告)日：2005-09-22

申请号：US11124709

申请日：2005-05-09

申请人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

发明人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3463 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

公开(公告)号：US20050127428A1

公开(公告)日：2005-06-16

申请号：US10732967

申请日：2003-12-10

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US20050099849A1

公开(公告)日：2005-05-12

申请号：US10703717

申请日：2003-11-07

申请人： Jeffrey Lutze ,  Chan-Sui Pang

发明人： Jeffrey Lutze ,  Chan-Sui Pang

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0425

摘要： A method for programming a storage element and a storage element programmed using gate induced junction leakage current are provided. The element may include at least a floating gate on a substrate, an active region in the substrate, and a second gate adjacent to the floating gate. The method may include the steps of: creating an inversion region in the substrate below the floating gate by biasing the first gate; and creating a critical electric field adjacent to the second gate. Creating a critical electric field may comprise applying a first positive bias to the active region; and applying a bias less than the first positive bias to the second gate. The element further includes a first bias greater than zero volts applied to the active region and a second bias greater than the first bias applied to the floating gate and a third bias less than or equal to zero applied to the second gate. The first and third bias are selected to create leakage current in the substrate between the floating gate and the select gate.

摘要翻译： 提供了一种用于编程存储元件的方法和使用栅极感应结漏电流编程的存储元件。 元件可以至少包括衬底上的浮动栅极，衬底中的有源区域和与浮置栅极相邻的第二栅极。 该方法可以包括以下步骤：通过偏置第一栅极在浮置栅极下方的衬底中产生反转区域; 并产生邻近第二栅极的临界电场。 创建临界电场可以包括将第一正偏压施加到有源区; 以及将小于所述第一正偏压的偏压施加到所述第二栅极。 元件还包括施加到有源区的大于零伏特的第一偏置和大于施加到浮置栅极的第一偏压的第二偏压和施加到第二栅极的小于或等于零的第三偏压。 选择第一和第三偏压以在浮置栅极和选择栅极之间的衬底中产生漏电流。

公开(公告)号：US20050083735A1

公开(公告)日：2005-04-21

申请号：US10689333

申请日：2003-10-20

申请人： Jian Chen ,  Jeffrey Lutze ,  Yan Li ,  Daniel Guterman ,  Tomoharu Tanaka

发明人： Jian Chen ,  Jeffrey Lutze ,  Yan Li ,  Daniel Guterman ,  Tomoharu Tanaka

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/12

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

摘要翻译： 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

公开(公告)号：US20050024943A1

公开(公告)日：2005-02-03

申请号：US10628962

申请日：2003-07-29

申请人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

发明人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

IPC分类号： G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/3454

摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

摘要翻译： 在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。 由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。 也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。 本发明包括确定存储器单元是否被过度编程。

公开(公告)号：US20050024939A1

公开(公告)日：2005-02-03

申请号：US10629068

申请日：2003-07-29

申请人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

发明人： Jian Chen ,  Yan Li ,  Jeffrey Lutze

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3463 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

摘要翻译： 在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。 由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。 也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。 本发明包括确定存储器单元是否被过度编程。

公开(公告)号：US08456915B2

公开(公告)日：2013-06-04

申请号：US13436805

申请日：2012-03-30

申请人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

发明人： Changyuan Chen ,  Jeffrey Lutze ,  Yingda Dong ,  Hua-Ling Hsu

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G10L15/26 ,  G11C2211/5621

摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

摘要翻译： 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标。 对被编程到一个或多个目标的第一组的非易失性存储元件进行验证以确定它们是否已经达到其目标，并且如果确定它们已经达到其目标，则被锁定进一步编程。 被编程到一个或多个目标的第二组的非易失性存储元件被测试以确定快速编程位的数量。 当特定目标的快速位数大于阈值时，则对于被编程到特定目标的非易失性存储元件的编程停止。

公开(公告)号：US08406053B1

公开(公告)日：2013-03-26

申请号：US13239194

申请日：2011-09-21

申请人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

发明人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

摘要翻译： 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。