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11.发明授权Structure for improving latch-up immunity and interwell isolation in a semiconductor device 失效用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构
公开(公告)号：US5831313A
公开(公告)日：1998-11-03
申请号：US698673
申请日：1996-08-15
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0921 , H01L21/76218 , H01L21/823878
摘要： A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.
摘要翻译： 提供一种用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构。 在一个实施例中，衬底具有形成在其中的上表面和第一掺杂区。 第一掺杂剂区域具有位于衬底的上表面下方的下边界和从衬底的上表面延伸到第一掺杂剂区域的下边界的边界。 具有分别沿着第一掺杂剂区域的下边界和边界定位的第一部分和第二部分的重掺杂区域具有大于第一掺杂剂区域的掺杂剂浓度的基本上均匀的掺杂剂浓度。 重掺杂区域提高了闩锁抗扰度和间隔隔离，而不会降低阈值电压容限。
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12.发明授权Selective diffusion process for forming both n-type and p-type gates with a single masking step 失效用于通过单个掩蔽步骤形成n型和p型栅极的选择性扩散过程
公开(公告)号：US5780330A
公开(公告)日：1998-07-14
申请号：US671984
申请日：1996-06-28
申请人： Jeong Yeol Choi
发明人： Jeong Yeol Choi
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , Y10S438/919
摘要： First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the polysilicon layer to cover a first region and expose a second region of the polysilicon layer. The exposed second region of the polysilicon layer is then counter-doped, with the first oxide layer acting as a mask to prevent counter-doping of the underlying first region of the polysilicon layer. In accordance with the present invention, n-channel devices with n-type or p-type polysilicon gates and p-channel devices with p-type or n-type polysilicon gates can be formed without having to add a single process step. Thus, n-channel and p-channel devices with two different threshold voltages can be realized without adding a single process step.
摘要翻译： 仅使用单个掩蔽步骤在多晶硅层中产生第一和第二导电类型区域。 在一个实施例中，多晶硅层掺杂到第一导电类型。 然后形成第一氧化物层并在多晶硅层上图案化以覆盖第一区域并暴露多晶硅层的第二区域。 然后对多晶硅层的暴露的第二区域进行反掺杂，其中第一氧化物层用作掩模以防止多晶硅层的下面的第一区域的反掺杂。 根据本发明，可以形成具有n型或p型多晶硅栅极的n沟道器件和具有p型或n型多晶硅栅极的p沟道器件，而不需要添加单个工艺步骤。 因此，可以在不添加单个工艺步骤的情况下实现具有两个不同阈值电压的n沟道和p沟道器件。
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公开(公告)号：US5750424A
公开(公告)日：1998-05-12
申请号：US764662
申请日：1996-12-10
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。
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公开(公告)号：US5654213A
公开(公告)日：1997-08-05
申请号：US538533
申请日：1995-10-03
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。
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15.发明授权Methods, apparatus and computer program products for modeling integrated circuit devices having reduced linewidths 失效用于对具有减小的线宽的集成电路器件进行建模的方法，装置和计算机程序产品公开(公告)号：US06898561B1
公开(公告)日：2005-05-24
申请号：US09465433
申请日：1999-12-21
申请人： Chunbo Liu , Zhijian Ma , Jeong Yeol Choi
发明人： Chunbo Liu , Zhijian Ma , Jeong Yeol Choi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods, apparatus and computer program products for modeling integrated circuits having dense devices therein that experience linewidth (e.g., gate electrodes) reductions during fabrication are provided. For dense devices having electrical paths therein and first and second gate electrodes that overlie the electrical path, operations include determining an electrical gate length of the first gate electrode by evaluating a change in current through the electrical path relative to a change in gate length of the second gate electrode. The operation to determine the electrical gate length of the first gate electrode includes evaluating a change in simulated drain-to-source current through the electrical path relative to a change in the electrical gate length of the second gate electrode.
摘要翻译： 提供了用于对其中具有密集器件的集成电路进行建模的方法，装置和计算机程序产品，其中制造中经历线宽（例如，栅电极）的减少。 对于其中具有电路径的密集器件以及覆盖电路的第一和第二栅电极，操作包括通过评估通过电路径的电流相对于栅极长度的变化来确定第一栅电极的电栅极长度 第二栅电极。 确定第一栅电极的电栅极长度的操作包括评估通过电路径的模拟漏极 - 源极电流相对于第二栅电极的电栅极长度的变化的变化。
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公开(公告)号：US06407008B1
公开(公告)日：2002-06-18
申请号：US09564786
申请日：2000-05-05
申请人： Yingbo Jia , Ohm-Guo Pan , Long-Ching Wang , Jeong Yeol Choi , Guo-Qiang (Patrick) Lo , Shih-Ked Lee
发明人： Yingbo Jia , Ohm-Guo Pan , Long-Ching Wang , Jeong Yeol Choi , Guo-Qiang (Patrick) Lo , Shih-Ked Lee
IPC分类号： H01L21314
CPC分类号： H01L21/28202 , C23C8/10 , C30B29/06 , C30B33/005 , H01L21/3144 , H01L21/31658 , H01L29/518
摘要： Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N2O and an inert gas such as argon or N2 is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.
摘要翻译： 通过快速热氧化在半导体器件中形成氮化氧化物的方法，其中具有暴露的硅表面的半导体衬底被放置在热处理室中。 然后，将包含N 2 O和惰性气体如氩气或N 2的环境气体引入处理室。 接下来，将硅表面加热到预定的工艺温度，从而氧化硅表面的至少一部分。 最后，冷却半导体衬底。 可以形成具有均匀氧化特性的超薄氧化物层，例如更多的硼渗透阻力，良好的氧化物组成和厚度均匀性，增加氧化物层中的电荷到击穿电压。
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公开(公告)号：US06127710A
公开(公告)日：2000-10-03
申请号：US900811
申请日：1997-07-25
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.
摘要翻译： 公开了CMOS结构，其中具有相反导电性的两个相邻的晶体管每个在它们各自的沟道区上方具有栅极。 其中一个晶体管的栅极不存在间隔。 该结构的特征还在于轻掺杂区域。
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18.发明授权Method for improving latch-up immunity and interwell isolation in a semiconductor device 失效用于提高半导体器件中的闩锁抗扰度和间隔隔离的方法
公开(公告)号：US6017785A
公开(公告)日：2000-01-25
申请号：US698675
申请日：1996-08-15
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0921 , H01L21/823878 , Y10S438/981
摘要： A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance. In alternative embodiments, one variable permeability mask is used to form the first dopant region and also to form the heavily doped region continuous with the first dopant region.
摘要翻译： 提供了一种提高半导体器件中的闩锁抗扰度和间隔隔离的方法。 在一个实施例中，在具有第一掺杂剂区域的衬底的表面上形成具有可植入杂质的可变磁导率的注入掩模。 注入掩模的第一部分覆盖第一掺杂区域的第一部分。 该结构经受高能量注入，其形成重掺杂区域。 重掺杂区域的第一部分沿着第一掺杂区域的下边界定位。 沿着第一掺杂剂区域的侧边界延伸的重掺杂区域的第二部分由穿过植入掩模的第一部分的杂质离子形成。 重掺杂区域提高了闩锁抗扰度和间隔隔离，而不会降低阈值电压容限。 在替代实施例中，使用一个可变磁导率掩模来形成第一掺杂区，并且还形成与第一掺杂区连续的重掺杂区。
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公开(公告)号：US5793088A
公开(公告)日：1998-08-11
申请号：US664440
申请日：1996-06-18
IPC分类号： H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/8238 , H01L27/0928 , H01L29/1033 , H01L29/1045 , H01L29/1083 , H01L29/6656
摘要： A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the underlying source/drain regions and into the edges of the halo regions which lie in the channel. The VT implant reduces junction capacitance and does not degrade punchthrough voltage.
摘要翻译： 提供了用于控制MOSFET的阈值电压的方法和结构。 该方法通过提供边缘阈值电压注入（VT注入）来补偿与现有技术的光晕植入物相关的边缘效应，该边缘阈值电压注入（VT注入）使杂质通过电介质间隔物穿过下面的源极/漏极区域并进入位于 这个频道。 VT注入降低结电容，不会降低穿通电压。
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