中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.016 seconds)

    QUADRATURE LC VOLTAGE CONTROLLED OSCILLATOR WITH OPPOSED BIAS AND COUPLING CONTROL STAGES
    11.
    发明申请
    QUADRATURE LC VOLTAGE CONTROLLED OSCILLATOR WITH OPPOSED BIAS AND COUPLING CONTROL STAGES 失效
    具有对准偏置和耦合控制阶段的LC电压控制振荡器

    公开(公告)号：US20080042754A1

    公开(公告)日：2008-02-21

    申请号：US11462180

    申请日：2006-08-03

    Applicant: Jinghong Chen

    Inventor： Jinghong Chen

    IPC: H03L7/00

    CPC classification number: H03L7/00 ,  H03B27/00 ,  H03L7/099

    Abstract: A voltage controlled oscillator unit is provided with cross coupled voltage controlled oscillators to generate quadrature phases. One control stage adjusts coupling between the oscillators. Another control stage adjusts the tail current that applies operating bias to the oscillators and to the couplers, respectively. The cross coupling and tail current control stages are arranged so that tuning one simultaneously and oppositely tunes the other for simultaneous adjustment in opposite directions. This limits the power consumption of the oscillator unit throughout the range of frequency control.

    Abstract translation: 压控振荡器单元设有交叉耦合电压控制振荡器以产生正交相位。 一个控制级调节振荡器之间的耦合。 另一个控制级分别调节向振荡器和耦合器施加工作偏压的尾电流。 交叉耦合和尾电流控制级被布置成使得调谐一个同时并相反地调谐另一个以在相反方向上同时进行调整。 这限制了整个频率控制范围内振荡器单元的功耗。

    HIGH-SPEED CML CIRCUIT DESIGN
    12.
    发明申请
    HIGH-SPEED CML CIRCUIT DESIGN 有权
    高速CML电路设计

    公开(公告)号：US20070018694A1

    公开(公告)日：2007-01-25

    申请号：US11421675

    申请日：2006-06-01

    Applicant: Jinghong Chen ,  Gregory Sheets ,  Lane Smith

    Inventor： Jinghong Chen ,  Gregory Sheets ,  Lane Smith

    IPC: H03K19/094

    CPC classification number: H03K19/09432 ,  H03K19/01707

    Abstract: A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

    Abstract translation: 提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。 负载耦合在电源节点和输出节点之间。 负载包括耦合到输出节点的折叠有源电感器。

    Low temperature curable materials for optical applications
    14.
    发明授权
    Low temperature curable materials for optical applications 有权
    用于光学应用的低温可固化材料

    公开(公告)号：US07445953B2

    公开(公告)日：2008-11-04

    申请号：US11192352

    申请日：2005-07-29

    Applicant: Victor Lu ,  Lei Jin ,  Arlene J. Suedmeyer ,  Paul G. Apen ,  Peter Alfred Smith ,  JingHong Chen

    Inventor： Victor Lu ,  Lei Jin ,  Arlene J. Suedmeyer ,  Paul G. Apen ,  Peter Alfred Smith ,  JingHong Chen

    IPC: H01L21/22

    CPC classification number: C09D183/04 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/316 ,  H01L27/1292

    Abstract: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices. A substantially crack-free and substantially void-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, a catalyst, and optionally water; (b) coating a substrate with the composition to form a film on the substrate, (c) crosslinking the composition by heating to produce a substantially crack-free and substantially void-free silicon polymer film, having a a transparency to light in the range of about 400 nm to about 800 nm of about 95% or more.

    Abstract translation: 本发明涉及可用于电子应用的低温可固化旋涂玻璃材料，例如光学器件。 通过（a）制备包含至少一种含硅预聚物，催化剂和任选的水的组合物来制备基本上无裂纹且基本上无空隙的硅聚合物膜; （b）用所述组合物涂覆基材以在基材上形成膜，（c）通过加热使组合物交联以产生基本上无裂纹且基本上无空隙的硅聚合物膜，其具有在 约400nm至约800nm约95％或更多。

    CML circuit devices having improved headroom
    15.
    发明授权
    CML circuit devices having improved headroom 失效
    CML电路器件具有改善的净空

    公开(公告)号：US07388406B2

    公开(公告)日：2008-06-17

    申请号：US11420098

    申请日：2006-05-24

    Applicant: Jinghong Chen

    Inventor： Jinghong Chen

    IPC: H03K19/20 ,  H03K19/094

    CPC classification number: H03K19/09432

    Abstract: A CML digital circuit includes a load coupled between a power supply node and at least one output node and a logic circuit component coupled to the output node. The logic circuit component has at least one data input node. The logic circuit component comprises a first circuit module and a second circuit module. A first tail current source is coupled to the first circuit module. A second tail current source is coupled to the second circuit module. A first switch is coupled between the power supply node and the first tail current source. A second switch is coupled between the power supply node and the second tail current source, wherein the first switch is triggered to deactivate the first circuit module when the second circuit module is operating and the second switch is triggered to deactivate the second circuit module when the first circuit module is operating.

    Abstract translation: CML数字电路包括耦合在电源节点和至少一个输出节点之间的负载以及耦合到输出节点的逻辑电路组件。 逻辑电路组件具有至少一个数据输入节点。 逻辑电路部件包括第一电路模块和第二电路模块。 第一尾电流源耦合到第一电路模块。 第二尾电流源耦合到第二电路模块。 第一开关耦合在电源节点和第一尾电流源之间。 第二开关耦合在电源节点和第二尾电流源之间，其中第一开关被触发以在第二电路模块工作时停用第一电路模块，并且当第二开关被触发时停用第二电路模块 第一个电路模块正在运行。

    MULTIPLE FREQUENCY GENERATOR FOR QUADRATURE AMPLITUDE MODULATED COMMUNICATIONS
    16.
    发明申请
    MULTIPLE FREQUENCY GENERATOR FOR QUADRATURE AMPLITUDE MODULATED COMMUNICATIONS 有权
    用于三角振幅调制通信的多频发生器

    公开(公告)号：US20080100387A1

    公开(公告)日：2008-05-01

    申请号：US11866766

    申请日：2007-10-03

    Applicant: Jinghong Chen ,  Chunbing Guo ,  Fuji Yang

    Inventor： Jinghong Chen ,  Chunbing Guo ,  Fuji Yang

    IPC: H03L7/085 ,  H03B21/02

    CPC classification number: H03B21/00 ,  H03B25/00 ,  H03L7/183 ,  H03L7/185 ,  H04L27/2637 ,  H04L27/2653

    Abstract: Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.

    Abstract translation: 多个载波频率从锁相环提供，特别是紧密相邻的正交幅度调制副载波，用于复用数据通信。 正交压控振荡器（VCO）和级联分频器向相位比较器提供反馈以将VCO锁定到参考信号。 除了用作子载波的分频器输出，例如VCO频率的二进制分频因子之外，正交混频器在两个频率上乘法并相加正交分量，以产生差分频率的差分信号。 混频器可以在反馈信号路径之外，但是优选地在反馈路径中以抑制噪声。 多相滤波器将混频器输出转换为可用作子载波的正交信号。 该技术有效地生成基本频率的顺序整数倍，例如频率参考的十六个相邻整数倍。

    Buffer with inductance-based capacitive-load reduction
    17.
    发明申请
    Buffer with inductance-based capacitive-load reduction 失效
    具有基于电感的电容负载减小的缓冲器

    公开(公告)号：US20080074149A1

    公开(公告)日：2008-03-27

    申请号：US11526306

    申请日：2006-09-25

    Applicant: Jinghong Chen

    Inventor： Jinghong Chen

    IPC: H03K19/094

    CPC classification number: H03F3/301 ,  H03F2203/30099 ,  H03F2203/30132

    Abstract: A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

    Abstract translation: 缓冲电路使用（例如，有源）电感器来驱动电容性负载。 在一个实施例中，缓冲电路具有一个或多个级，每级具有一个CMOS反相器。 每个CMOS反相器具有一个NMOS晶体管和一个PMOS晶体管，并且耦合到级输入和级输出。 此外，缓冲电路的至少一级具有两个电感器，每个电感耦合在用于缓冲电路的不同参考电压和级输出之间。 一个电感器具有耦合到NMOS晶体管的栅极的PMOS晶体管，另一个电感器具有耦合到PMOS晶体管的栅极的NMOS晶体管。 当驱动容性负载时，电感器部分地调出视在负载电容CL，从而提高逆变器的充电能力，并且能够实现更快的充电和放电时间。 此外，部分调谐视在负载电容有助于驱动较大的容性负载。

    Thick crack-free silica film by colloidal silica incorporation
    18.
    发明申请
    Thick crack-free silica film by colloidal silica incorporation 审中-公开
    通过胶体二氧化硅掺入的无裂纹二氧化硅薄膜

    公开(公告)号：US20070099005A1

    公开(公告)日：2007-05-03

    申请号：US11262588

    申请日：2005-10-31

    Applicant: Roger Leung ,  Jan Nedbal ,  Jinghong Chen ,  Amanuel Gebrebrhan ,  Beth Munoz

    Inventor： Roger Leung ,  Jan Nedbal ,  Jinghong Chen ,  Amanuel Gebrebrhan ,  Beth Munoz

    IPC: B32B9/04 ,  C08G77/08

    CPC classification number: C08L83/04 ,  C08K3/36 ,  C09D183/04 ,  H01B3/04 ,  Y10T428/31612 ,  Y10T428/31663 ,  C08L2666/58 ,  C08L2666/54

    Abstract: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices, in particular for flat panel displays. A substantially crack-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, colloidal silica, an optional catalyst, and optional water; (b) coating a substrate with the composition to form a film on the substrate, (c) crosslinking the composition by heating to produce a substantially crack-free silicon polymer film, having a thickness of from about 700 Å to about 20,000 Å, and a transparency to light in the range of about 400 nm to about 800 nm of about 90% or more.

    Abstract translation: 本发明涉及可用于电子应用的低温可固化旋涂玻璃材料，例如光学装置，特别是用于平板显示器。 通过（a）制备包含至少一种含硅预聚物，胶体二氧化硅，任选的催化剂和任选的水的组合物来制备基本上无裂纹的硅聚合物膜; （b）用所述组合物涂覆基材以在基材上形成膜，（c）通过加热使组合物交联以产生具有约700至约20,000的厚度的基本上无裂纹的硅聚合物膜，以及 在约400nm至约800nm的范围内的光的透明度为约90％或更多。

    Low temperature curable materials for optical applications
    19.
    发明申请
    Low temperature curable materials for optical applications 有权
    用于光学应用的低温可固化材料

    公开(公告)号：US20060035419A1

    公开(公告)日：2006-02-16

    申请号：US11192352

    申请日：2005-07-29

    Applicant: Victor Lu ,  Lei Jin ,  Arlene Suedmeyer ,  Paul Apen ,  Peter Smith ,  Jinghong Chen

    Inventor： Victor Lu ,  Lei Jin ,  Arlene Suedmeyer ,  Paul Apen ,  Peter Smith ,  Jinghong Chen

    IPC: H01L21/84 ,  H01L21/31

    CPC classification number: C09D183/04 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/316 ,  H01L27/1292

    Abstract: The invention relates to low temperature curable spin-on glass materials which are useful for electronic applications, such as optical devices. A substantially crack-free and substantially void-free silicon polymer film is produced by (a) preparing a composition comprising at least one silicon containing pre-polymer, a catalyst, and optionally water; (b) coating a substrate with the composition to form a film on the substrate, (c) crosslinking the composition by heating to produce a substantially crack-free and substantially void-free silicon polymer film, having a a transparency to light in the range of about 400 nm to about 800 nm of about 95% or more.

    Abstract translation: 本发明涉及可用于电子应用的低温可固化旋涂玻璃材料，例如光学器件。 通过（a）制备包含至少一种含硅预聚物，催化剂和任选的水的组合物来制备基本上无裂纹且基本上无空隙的硅聚合物膜; （b）用所述组合物涂覆基材以在基材上形成膜，（c）通过加热使组合物交联以产生基本上无裂纹且基本上无空隙的硅聚合物膜，其具有在 约400nm至约800nm约95％或更多。

Patent Agency Ranking