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公开(公告)号：US09329871B2
公开(公告)日：2016-05-03
申请号：US13608192
申请日：2012-09-10
Applicant: Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC: H04N7/18 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/91 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/423 , H04N19/90 , H04N19/625
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
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公开(公告)号：US08831093B2
公开(公告)日：2014-09-09
申请号：US13437183
申请日：2012-04-02
Applicant: Ilie Garbacea , Lulin Chen , Jose R. Alvarez
Inventor： Ilie Garbacea , Lulin Chen , Jose R. Alvarez
IPC: H04B1/66 , H04N19/176 , H04N19/14 , H04N19/126 , H04N11/04
CPC classification number: H04N19/00096 , H04N19/126 , H04N19/14 , H04N19/176
Abstract: In some embodiments, macroblock-level encoding parameters are assigned to weighted linear combinations of corresponding content-category-level encoding parameters. For example, a macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.
Abstract translation: 在一些实施例中，将宏块级编码参数分配给对应的内容类别级编码参数的加权线性组合。 例如，将宏块量化参数（QP）调制设置为内容类型QP调制的加权线性组合。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合块级统计信息生成内容类别级统计信息。 内容类别级统计可用于对后续帧进行编码。
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公开(公告)号：US08803995B2
公开(公告)日：2014-08-12
申请号：US12979550
申请日：2010-12-28
Applicant: Jose R. Alvarez , Guy Cote
Inventor： Jose R. Alvarez , Guy Cote
CPC classification number: H04N19/59 , H04N19/117 , H04N19/124 , H04N19/132 , H04N19/14 , H04N19/146 , H04N19/17 , H04N19/176 , H04N19/61 , H04N19/85
Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit.
Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为使用编码相关信息来执行图像信号处理。 第二电路可以被配置为使用图像信号处理相关信息对图像数据进行编码，其中所述第一电路还被配置为将所述图像信号处理相关信息传递到所述第二电路，并且所述第二电路还被配置为将所述编码相关信息传递到 说第一个电路。
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公开(公告)号：US20130022105A1
公开(公告)日：2013-01-24
申请号：US13608221
申请日：2012-09-10
Applicant: Alexander G. MacInnis , Jose' R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Alexander G. MacInnis , Jose' R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC: H04N7/12
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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公开(公告)号：US08284844B2
公开(公告)日：2012-10-09
申请号：US10114798
申请日：2002-04-01
Applicant: Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Alexander G. MacInnis , Jose′ R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC: H04N7/18
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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Patent Agency Ranking
公开(公告)号：US20120020412A1
公开(公告)日：2012-01-26
申请号：US13205776
申请日：2011-08-09
Applicant: Jose R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Jose R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/13 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
Abstract translation: 一种用于解码数字视频数据流的系统和方法。 在一个方面，多个硬件加速模块与核心处理器一起使用。 加速器在解码管线中操作，其中在任何给定阶段，每个加速器对视频数据的特定宏块进行操作。 在随后的流水线阶段，每个加速器对数据流中的下一个宏块进行工作，该前一阶段的另一个加速器工作。 核心处理器在每个阶段轮询所有加速器。 当所有加速器在给定阶段完成任务时，核心处理器启动下一阶段。 在另一方面，采用两个可变长度解码器来同时解码视频帧的两个宏块行。 每个可变长度解码器用于对分配的行进行解码，并行并行地进行可变长度解码。 可变长度解码器作为流水线的一部分进行操作，其中可变长度解码器逐级交替解码宏块。
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公开(公告)号：US09104424B2
公开(公告)日：2015-08-11
申请号：US13205776
申请日：2011-08-09
Applicant: Jose R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Jose R. Alvarez , Alexander G. MacInnis , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
IPC: H04N7/18 , G06F9/38 , H04N19/176 , H04N19/70 , H04N19/13 , H04N19/122 , H04N19/129 , H04N19/61 , H04N19/60 , H04N19/12 , H04N19/157 , H04N19/44 , H04N19/82 , H04N19/423 , H04N19/90
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/13 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/82 , H04N19/90
Abstract: A system and method for decoding a digital video data stream. In one aspect, a plurality of hardware acceleration modules are used together with a core processor. The accelerators operate in a decoding pipeline wherein, in any given stage, each accelerator operates on a particular macroblock of video data. In the subsequent pipeline stage, each accelerator works on the next macroblock in the data stream, which was worked on by another one of the accelerators in the previous stage. The core processor polls all of the accelerators during each stage. When all accelerators finish their tasks for a given stage, the core processor initiates the next stage. In another aspect, two variable-length decoders are employed to simultaneously decode two macroblock rows of a video frame. Each variable-length decoder works to decode an assigned row and the rows are variable-length decoded in parallel. The variable-length decoders operate as part of a pipeline wherein the variable-length decoders alternate, stage-by-stage, decoding macroblocks.
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公开(公告)号：US08081682B1
公开(公告)日：2011-12-20
申请号：US11250109
申请日：2005-10-13
Applicant: Ilie Carbacea , Lulin Chen , Jose R. Alvarez
Inventor： Ilie Carbacea , Lulin Chen , Jose R. Alvarez
CPC classification number: H04N19/85 , H04N19/107 , H04N19/109 , H04N19/11 , H04N19/124 , H04N19/136 , H04N19/176 , H04N19/61
Abstract: In some embodiments, encoding modes for a video image block are enabled according to similarity measures of the block with respect to multiple content categories. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. In a priority mode, the encoding modes specified by a priority content category (e.g. a red category) are selectively enabled for the block, regardless of the block's similarity to other (non-priority) content categories, provided the block is sufficiently similar to the priority category. In a dominant mode, the encoding modes enabled by a maximum-similarity content category are enabled for the block. In an all-inclusive mode, any mode enabled by any sufficiently-similar content category is enabled for the block. Enabled encoding modes may be further evaluated for selection for the block. Encoding modes may include inter/intra modes, macroblock partition sizes, and intra-prediction directions.
Abstract translation: 在一些实施例中，视频图像块的编码模式根据块相对于多个内容类别的相似性度量被启用。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 在优先模式中，无论块与其他（非优先级）内容类别的相似度如何，只要块与...相似，就可以选择性地启用优先级内容类别（例如，红色类别）指定的编码模式 优先类别。 在主导模式中，通过最大相似内容类别启用的编码模式对于块是启用的。 在全包模式下，对于该块，启用任何类似相似内容的任何模式。 可以对块的选择进一步评估启用的编码模式。 编码模式可以包括帧间/帧内模式，宏块分区大小和帧内预测方向。
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公开(公告)号：US20110122941A1
公开(公告)日：2011-05-26
申请号：US13018840
申请日：2011-02-01
Applicant: Alexander G. MacInnis , Jose R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
Inventor： Alexander G. MacInnis , Jose R. Alvarez , Sheng Zhong , Xiaodong Xie , Vivian Hsiun
CPC classification number: G06F9/3861 , G06F9/3877 , H04N19/12 , H04N19/122 , H04N19/129 , H04N19/157 , H04N19/176 , H04N19/423 , H04N19/44 , H04N19/60 , H04N19/61 , H04N19/625 , H04N19/70 , H04N19/82 , H04N19/90 , H04N19/91
Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.
Abstract translation: 用于解码数字视频数据的系统和方法。 解码系统采用辅助核心处理器执行所选解码任务的硬件加速器。 硬件加速器可配置为支持多种现有和将来的编码/解码格式。 加速器可配置为支持落入基于DCT的熵解码的块运动补偿压缩算法的一般类别中的任何现有或将来的编码/解码格式。 硬件加速器示例性地包括可编程熵解码器，逆量化模块，反相离散余弦变换模块，像素滤波器，运动补偿模块和去块滤波器。 硬件加速器在解码流水线中起作用，其中在流水线中的任何给定阶段，在给定宏块上执行给定功能的同时，数据流中的下一个宏块正在通过管道中的先前功能进行处理。
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20.发明授权Method and/or apparatus for detecting edges of blocks in an image processing system 失效用于检测图像处理系统中块的边缘的方法和/或装置公开(公告)号：US07590288B1
公开(公告)日：2009-09-15
申请号：US11268130
申请日：2005-11-07
Applicant: Jose R. Alvarez , Huipin Zhang
Inventor： Jose R. Alvarez , Huipin Zhang
CPC classification number: G06K9/4619 , G06T7/13 , G06T7/181 , G06T2207/10016
Abstract: An apparatus comprising an edge detector circuit, an edge strength detector and an edge strength threshold circuit. The edge detector circuit may be configured to determine a plurality of default directions of a macroblock in response to a plurality of input signals comprising information about a plurality of samples in the macroblock. The edge strength detector circuit may be configured to generate a maximum strength signal and a next maximum strength signal in response to the default directions. The edge strength threshold circuit may be configured to generate an edge direction signal and an edge strength signal in response to the maximum strength signal and the next maximum strength signal. The edge direction signal may comprise (i) any one of the default directions when in a first state and (ii) any one of a plurality of intermediate directions when in a second state.
Abstract translation: 一种包括边缘检测器电路，边缘强度检测器和边缘强度阈值电路的装置。 边缘检测器电路可以被配置为响应于包括关于宏块中的多个采样的信息的多个输入信号来确定宏块的多个默认方向。 边缘强度检测器电路可以被配置为响应于默认方向产生最大强度信号和下一个最大强度信号。 边缘强度阈值电路可以被配置为响应于最大强度信号和下一最大强度信号而产生边缘方向信号和边缘强度信号。 边缘方向信号可以包括（i）处于第一状态时的默认方向中的任何一个，以及当处于第二状态时，（ii）多个中间方向中的任何一个。
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