Adaptive crawl rates based on publication frequency
    11.
    发明授权
    Adaptive crawl rates based on publication frequency 有权
    基于出版频率的自适应爬网率

    公开(公告)号:US08255385B1

    公开(公告)日:2012-08-28

    申请号:US13053772

    申请日:2011-03-22

    IPC分类号: G06F7/00 G06F17/30

    CPC分类号: G06F17/3089

    摘要: Methods and systems for determining an adaptive crawl rate for a Web crawler based on historical publication data from a Web source are provided. A frequency of publication of the Web source is determined over a specified period of time, and an adaptive crawl rate is calculated using the frequency of publication. The Web crawler is then deployed at the calculated adaptive crawl rate.

    摘要翻译: 提供了基于Web源的历史发布数据来确定Web爬虫的自适应爬网速率的方法和系统。 在指定的时间段内确定Web源的发布频率,并使用发布频率计算自适应爬网速率。 然后以计算的自适应爬网率部署Web爬虫。

    Fluoride-modified silica sols for chemical mechanical planarization
    12.
    发明授权
    Fluoride-modified silica sols for chemical mechanical planarization 失效
    用于化学机械平面化的氟化物改性硅溶胶

    公开(公告)号:US08163049B2

    公开(公告)日:2012-04-24

    申请号:US11783191

    申请日:2007-04-06

    IPC分类号: B24D3/02 C09C1/68 C09K3/14

    摘要: A chemical-mechanical planarization composition containing surface-modified abrasive particles such as silica where at least a portion of the surface of the particles has bound thereto a surface-modifying aluminum-containing stabilizer and fluoride that is used to polish semiconductor substrates. The use of a CMP slurry containing surface-modifying aluminum-containing stabilizer and fluoride bound to a silica abrasive provides high metal polishing rates relative to the removal rate of a dielectric.

    摘要翻译: 含有表面改性的磨料颗粒如二氧化硅的化学机械平面化组合物,其中颗粒表面的至少一部分与表面改性的含铝稳定剂结合,用于抛光半导体衬底的氟化物。 使用含有表面改性的含铝稳定剂和结合到二氧化硅研磨剂的氟化物的CMP浆料相对于电介质的去除速率提供了高的金属抛光速率。

    ENHANCING FRESHNESS OF SEARCH RESULTS
    13.
    发明申请
    ENHANCING FRESHNESS OF SEARCH RESULTS 有权
    增强搜索结果的清晰度

    公开(公告)号:US20110295844A1

    公开(公告)日:2011-12-01

    申请号:US12789020

    申请日:2010-05-27

    IPC分类号: G06F17/30

    摘要: Methods, systems, and computer-storage media for improving the freshness, or the apparent freshness, of search results are described. In an embodiment, the first portion of search results presented on a search results page are based on responsiveness to the search query and a second portion of results describe only recently published documents that are responsive to the search query. In an embodiment, a more recent version of the document, which is not directly used to determine responsiveness, is used to build the caption for a search result. Another way to make search results appear fresh is to include a publication time within the search result caption. In one embodiment, the publication time is generated by calculating a point in time between when a document is first added to a search index and the previous time the search engine visited the site where the document was found.

    摘要翻译: 描述了用于提高搜索结果的新鲜度或表观新鲜度的方法,系统和计算机存储介质。 在一个实施例中,在搜索结果页面上呈现的搜索结果的第一部分基于对搜索查询的响应,并且结果的第二部分仅描述响应于搜索查询的最近发布的文档。 在一个实施例中,使用不直接用于确定响应性的文档的更新版本来构建搜索结果的标题。 使搜索结果显示新鲜的另一种方法是在搜索结果标题中包含发布时间。 在一个实施例中,发布时间是通过计算文档首次添加到搜索索引的时间点与搜索引擎访问该文档所在的站点的之前的时间点来生成的。

    Method for Chemical Mechanical Planarization of Chalcogenide Materials
    15.
    发明申请
    Method for Chemical Mechanical Planarization of Chalcogenide Materials 有权
    硫族化物材料化学机械平面化方法

    公开(公告)号:US20090057661A1

    公开(公告)日:2009-03-05

    申请号:US12193303

    申请日:2008-08-18

    IPC分类号: H01L21/306 H01L29/12

    摘要: A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels (e.g., scratches incurred during polishing) as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.

    摘要翻译: 描述了含硫族化物的衬底(例如,含锗/锑(碲(GST))衬底的化学机械平面化的方法和相关组合物)。 组合物和方法在CMP处理期间提供低缺陷水平(例如抛光期间产生的划痕)以及含硫属化物的衬底的低凹陷和局部侵蚀水平。

    Reverse Shallow Trench Isolation Process
    16.
    发明申请
    Reverse Shallow Trench Isolation Process 审中-公开
    反向浅沟槽隔离工艺

    公开(公告)号:US20090047870A1

    公开(公告)日:2009-02-19

    申请号:US12179643

    申请日:2008-07-25

    IPC分类号: B24B1/00 B24B29/00

    CPC分类号: C09G1/02 B24B37/044

    摘要: A method of polishing a substrate surface containing silicon nitride and silicon oxide or silicon dioxide, comprising movably contacting the surface with a polishing pad and having a polishing composition disposed between the polishing pad and the surface, said polishing composition comprising 1) hydrous ceria abrasive; 2) polyvinylpyridine, vinyl pyridine copolymers, or both, and 3) water, wherein at 2 psi downpressure the silicon nitride removal rate is at least 500 angstroms per minute and the selectivity of silicon nitride to silicon oxide is at least 30.

    摘要翻译: 一种抛光含有氮化硅和氧化硅或二氧化硅的衬底表面的方法,包括使表面与抛光垫可移动地接触并且具有设置在抛光垫和表面之间的抛光组合物,所述抛光组合物包含1)含水二氧化铈磨料; 2)聚乙烯基吡啶,乙烯基吡啶共聚物或两者,以及3)水,其中在2psi的压力下,氮化硅去除速率为至少500埃/分钟,并且氮化硅与氧化硅的选择性为至少30。

    Five volt tolerant TTL/CMOS and CMOS/CMOS voltage conversion circuit
    20.
    发明授权
    Five volt tolerant TTL/CMOS and CMOS/CMOS voltage conversion circuit 失效
    五伏宽TTL / CMOS和CMOS / CMOS电压转换电路

    公开(公告)号:US5883528A

    公开(公告)日:1999-03-16

    申请号:US822375

    申请日:1997-03-20

    IPC分类号: H03K19/0185 H03K19/0948

    CPC分类号: H03K19/018585

    摘要: An input circuit to a semiconductor device may selectively accept different voltage logic levels (e.g., TTL or CMOS) as selected by a preset selection signal. The selection signal activates an N-type or P-type transistor in the input circuit which alters the threshold switching voltage of the input circuit logic. By altering the input threshold voltage, both TTL and CMOS input signals may be correctly triggered. An additional circuitry may be provided to allow a low voltage circuit (e.g., 3.3 Volts) to be tolerant of higher voltage inputs (e.g., 5 Volts). An isolation transistor isolates the input of the circuit from the high voltage signal, while a pulldown transistor pulls a high logic, high voltage signal down to supply voltage level.

    摘要翻译: 到半导体器件的输入电路可以选择性地接受由预设选择信号选择的不同的电压逻辑电平(例如,TTL或CMOS)。 选择信号激活输入电路中的N型或P型晶体管,其改变输入电路逻辑的阈值切换电压。 通过改变输入阈值电压,可以正确地触发TTL和CMOS输入信号。 可以提供额外的电路以允许低电压电路(例如,3.3伏特)容忍较高电压输入(例如,5伏特)。 隔离晶体管将电路的输入与高压信号隔离,而下拉晶体管将高逻辑高电压信号降低至电源电压电平。