公开(公告)号：US20080124931A1

公开(公告)日：2008-05-29

申请号：US11978718

申请日：2007-10-30

Applicant: Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

Inventor： Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

IPC: H01L21/302

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838

Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.

Abstract translation: 用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度 在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案， 在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为 蚀刻掩模以形成蚀刻膜图案。

公开(公告)号：US07375390B2

公开(公告)日：2008-05-20

申请号：US11621617

申请日：2007-01-10

Applicant: Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

Inventor： Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract translation: 半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离 在一行中等于相邻行中的活动区域之间的距离。

公开(公告)号：US20080070361A1

公开(公告)日：2008-03-20

申请号：US11898667

申请日：2007-09-14

Applicant: Kwang-Sub Yoon ,  Jung-Hyeon Lee ,  Bong-Cheol Kim ,  Se-Young Park

Inventor： Kwang-Sub Yoon ,  Jung-Hyeon Lee ,  Bong-Cheol Kim ,  Se-Young Park

IPC: H01L21/8242 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.

Abstract translation: 在制造电容器的方法和制造动态随机存取存储器件的方法中，覆盖导电层的上部的绝缘层可以设置有臭氧气体，以便改变绝缘材料的上部的性质 层。 可以化学去除绝缘层的上部以暴露导电层的上部。 可以去除暴露的导电层的上部，以便将导电层转变成下电极。 可以除去绝缘层的剩余部分，并且可以在下电极上形成上电极。

公开(公告)号：US20080052660A1

公开(公告)日：2008-02-28

申请号：US11830265

申请日：2007-07-30

Applicant: Woo-seok SHIM ,  Moon-Hyun YOO ,  Chun-Suk SUH ,  Jung-Hyeon LEE ,  Ji-Suk HONG ,  Yong-Hee PARK

Inventor： Woo-seok SHIM ,  Moon-Hyun YOO ,  Chun-Suk SUH ,  Jung-Hyeon LEE ,  Ji-Suk HONG ,  Yong-Hee PARK

IPC: G03F1/00 ,  G06F17/50

CPC classification number: G03F1/36

Abstract: A method of correcting a design pattern of a mask takes into account the overlay margin between adjacent one of actual patterns that are stacked on a substrate. First, a pattern of a photomask for forming a first one of the actual patterns on a substrate is conceived. Also, information representing the image of a second one of the actual patterns is produced. Then, optical proximity correction (OPC) is performed on the first pattern based on the information. The information may be obtained by simulating the transcription of a photomask having a second pattern designed to form the second actual pattern, or by forming the second actual pattern and then capturing the image of the second actual pattern. Accordingly, a sufficient margin is provided between the second actual pattern and the first pattern on which the optical proximity correction has been performed.

Abstract translation: 校正掩模的设计图案的方法考虑了堆叠在基板上的相邻的一个实际图案之间的覆盖边缘。 首先，设想用于在基板上形成第一种实际图案的光掩模图案。 此外，产生表示第二实际图案的图像的信息。 然后，基于该信息对第一图案执行光学邻近校正（OPC）。 可以通过模拟具有被设计为形成第二实际图案的第二图案的光掩模的转录或通过形成第二实际图案然后捕获第二实际图案的图像来获得信息。 因此，在第二实际图案和已进行光学邻近校正的第一图案之间提供足够的余量。

公开(公告)号：US20050035387A1

公开(公告)日：2005-02-17

申请号：US10918175

申请日：2004-08-13

Applicant: Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

Inventor： Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

IPC: H01L27/04 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract translation: 半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离 在一行中等于相邻行中的活动区域之间的距离。

公开(公告)号：US06716746B1

公开(公告)日：2004-04-06

申请号：US09640754

申请日：2000-08-18

Applicant: In Sung Kim ,  Joon Soo Park ,  Jung Hyeon Lee ,  Hyun Jae Kang

Inventor： In Sung Kim ,  Joon Soo Park ,  Jung Hyeon Lee ,  Hyun Jae Kang

IPC: H01L214763

CPC classification number: H01L21/76897

Abstract: A semiconductor device includes a conductive region and line, and a contact plug electrically connecting the line and the region. The line is connected to the region via sidewalls of the plug, and the region is connected to the line via the bottom of the plug. The cross-sectional area of the plug decreases in a direction from an upper to lower portion thereof. In a first method of fabricating a semiconductor device having a self-aligned contact, the plug is formed after the line is formed in an interlayer dielectric layer. Portions of the dielectric layer and line are etched to form a contact hole in which the plug is formed. In a second method, a line having a gap therein is formed in an interlayer dielectric layer. Portions of the dielectric layer, including the gap in the line, are etched to form the contact hole.

Abstract translation: 半导体器件包括导电区域和线路，以及电连接线路和区域的接触插头。 线路通过插头的侧壁连接到该区域，并且该区域经由插头的底部连接到线路。 塞子的横截面积从其上部向下部的方向减小。 在制造具有自对准接触的半导体器件的第一种方法中，在将线形成在层间电介质层中之后形成插塞。 蚀刻电介质层和线的一部分以形成其中形成插头的接触孔。 在第二种方法中，在层间绝缘层中形成具有间隙的线。 包括线中的间隙的电介质层的一部分被蚀刻以形成接触孔。

公开(公告)号：US20090274980A1

公开(公告)日：2009-11-05

申请号：US12267687

申请日：2008-11-10

Applicant: Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

Inventor： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

IPC: G03F7/20

CPC classification number: H01L21/027 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

Abstract translation: 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中，在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中，在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

公开(公告)号：US07449383B2

公开(公告)日：2008-11-11

申请号：US11898667

申请日：2007-09-14

Applicant: Kwang-Sub Yoon ,  Jung-Hyeon Lee ,  Bong-Cheol Kim ,  Se-Young Park

Inventor： Kwang-Sub Yoon ,  Jung-Hyeon Lee ,  Bong-Cheol Kim ,  Se-Young Park

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.

公开(公告)号：US07205241B2

公开(公告)日：2007-04-17

申请号：US10731931

申请日：2003-12-10

Applicant: Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

Inventor： Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

IPC: H01L21/302

CPC classification number: H01L21/76897 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/91 ,  Y10S438/942

Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

Abstract translation: 提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。 在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接 第一绝缘层。 此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。 此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

公开(公告)号：US20060115954A1

公开(公告)日：2006-06-01

申请号：US11265937

申请日：2005-11-03

Applicant: Woo-Seok Shim ,  Young-Wook Park ,  Jung-Hyeon Lee ,  Kwang-Sub Yoon ,  Chul-Ho Kim ,  Tae-Jin Park

Inventor： Woo-Seok Shim ,  Young-Wook Park ,  Jung-Hyeon Lee ,  Kwang-Sub Yoon ,  Chul-Ho Kim ,  Tae-Jin Park

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: In methods of manufacturing a capacitor and a semiconductor device, a mold layer is formed on a substrate having a contact plug. The mold layer includes an opening exposing the contact plug. A conductive layer is formed on the contact plug, an inner sidewall of the opening and the mold layer. A photoresist pattern is formed to substantially fill the opening. A cylindrical lower electrode is formed by partially removing the conductive layer. The mold layer is selectively removed while the photoresist pattern prevents damage to the lower electrode, the contact plug and the substrate. The photoresist pattern is removed, and then a dielectric layer and an upper electrode are sequentially formed on the lower electrode. Damage to the lower electrode and the contact plug are effectively prevented due to the presence of the photoresist pattern during selective removal of the mold layer.

Abstract translation: 在制造电容器和半导体器件的方法中，在具有接触插塞的基板上形成模层。 模具层包括露出接触塞的开口。 在接触插塞，开口的内侧壁和模具层上形成导电层。 形成光致抗蚀剂图案以基本上填充开口。 通过部分去除导电层形成圆柱形下电极。 选择性地去除模具层，同时光刻胶图案防止损坏下部电极，接触插塞和基板。 去除光致抗蚀剂图案，然后在下电极上依次形成电介质层和上电极。 由于在选择性去除模具层期间存在光致抗蚀剂图案，因此有效地防止了下电极和接触插塞的损坏。