公开(公告)号：US5862144A

公开(公告)日：1999-01-19

申请号：US956913

申请日：1997-10-23

Applicant: Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: G01R23/00 ,  G01R27/32 ,  G06F11/00

CPC classification number: G01R27/32

Abstract: A method for correcting a high frequency measurement error which can exactly correct the high frequency measurement error even with the use of a standard devices of which characteristic have not been verified by calculating the characteristic impedance of the correction device from the characteristics of an auxiliary measuring device calculated by using a general error correction method, and calculating again the once calculated characteristics of the auxiliary measuring device. The method in accordance with the present invention comprises the steps of modelling an auxiliary measuring device used for measuring a high frequency charateristics of the device under test by two transmission lines connected in series between two terminals and a parasitic component connected in parallel between a junction of the two transmission lines and a ground; and moving a reference measurement point to the junction of the two transmission lines by using a phase angle of each transmission line and calculating a reference impedance at the terminal of the auxiliary measuring device to which an object to be measured is connected by using the difference of the resultant reflection coefficients of each port.

Abstract translation: 一种用于校正高频测量误差的方法，即使使用通过从辅助测量装置的特性计算校正装置的特性阻抗尚未验证其特性的标准装置，也可以精确地校正高频测量误差 通过使用通用误差校正方法计算，并再次计算辅助测量装置的一次计算的特性。 根据本发明的方法包括以下步骤：对用于测量被测器件的高频特性的两个传输线串联连接在两个端子之间的辅助测量装置和在两个端子之间并联连接的寄生元件进行建模， 两条传输线和一条地面; 并且通过使用每个传输线的相位角将参考测量点移动到两个传输线的结点，并且通过使用所述差异来计算被测量对象的辅助测量装置的端子处的基准阻抗 每个端口的反射系数。

公开(公告)号：US5668022A

公开(公告)日：1997-09-16

申请号：US700930

申请日：1996-08-23

Applicant: Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

Inventor： Deok-Ho Cho ,  Soo-Min Lee ,  Tae-Hyeon Han ,  Byung-Ryul Ryum ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: A silicon/silicon-germanium bipolar transistor fabrication method employs a metallic silicide film as an extrinsic base electrode to reduce resistance of the extrinsic base electrode, and to increase a maximum oscillation frequency and cut-off frequency due to its self-aligned structure. The fabrication method enables agglomeration to occur on the side wall of the polycrystalline silicon film connected to the metallic silicide film instead of on the interface between the metallic silicide film and the lower silicon/silicon-germanium film, and leads the extrinsic base electrode to be sandwitched by the insulator films, thereby realizing a constant resistance and also resulting in the application of integrated circuits to a mass production mechanism.

Abstract translation: 硅/硅 - 锗双极晶体管制造方法使用金属硅化物膜作为外部基极，以降低外部基极的电阻，并且由于其自对准结构而增加最大振荡频率和截止频率。 该制造方法可以在连接到金属硅化物膜的多晶硅膜的侧壁上而不是在金属硅化物膜和下硅/硅 - 锗膜之间的界面上发生聚集，并且引导外部基极为 由绝缘体膜切割，从而实现恒定的电阻，并且还导致集成电路应用于大规模生产机构。

公开(公告)号：US06204102B1

公开(公告)日：2001-03-20

申请号：US09207512

申请日：1998-12-09

Applicant: Hyung Sup Yoon ,  Jin Hee Lee ,  Byung Sun Park ,  Chul Soon Park ,  Kwang Eui Pyun

Inventor： Hyung Sup Yoon ,  Jin Hee Lee ,  Byung Sun Park ,  Chul Soon Park ,  Kwang Eui Pyun

IPC: H01L21338

CPC classification number: B82Y10/00 ,  H01L21/28587 ,  H01L29/66469 ,  H01L29/66878

Abstract: A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

Abstract translation: 一种形成化合物半导体器件的栅电极的方法包括：形成具有第一孔的第一绝缘膜图案，在第一绝缘膜图案上形成具有由反V型构成的第二孔的第二绝缘膜图案，形成T 通过在整个结构上沉积导电膜，去除第二绝缘膜图案，通过蚀刻第一绝缘膜图案在极侧壁上形成绝缘隔离物，并通过自发形成源极和漏极的欧姆电极， 使用T型栅电极作为掩模的对准方法。 因此，通过使用绝缘膜，可以防止诸如难熔金属的材料的T型栅极电极由于高退火而被稳定地形成。 通过自对准方法形成的欧姆金属和栅电极可以通过在这些电极之间形成绝缘膜间隔来防止互连。

公开(公告)号：US5970328A

公开(公告)日：1999-10-19

申请号：US961407

申请日：1997-10-30

Applicant: Byung-Sun Park ,  Jin-Hee Lee ,  Hyung-Sup Yoon ,  Chul-Sun Park ,  Kwang-Eui Pyun

Inventor： Byung-Sun Park ,  Jin-Hee Lee ,  Hyung-Sup Yoon ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L21/338

CPC classification number: H01L29/66462 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/42316

Abstract: A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film. A leg of the gate electrode is formed at the portion of the dummy pattern. According to the present invention, a step for improving the resolution is not required, and a gate electrode having a very fine line width of a few hundreds .ANG. can be obtained by regulating the thickness of the silicon nitride film.

Abstract translation: 一种用于制造诸如HEMT的高速半导体器件的T形栅极的方法，其应用于包括具有X频带或更多频率的低噪声接收机和功率放大器的高速逻辑电路，以及具有 毫米波段的频率。 这样的器件需要栅极长度短和栅极图案的大截面积。 常规的光刻技术需要用于制造细线宽度的分辨率。 因此，电子束光刻被广泛使用。 但是，由于在使用电子束的方法中需要大量的曝光时间，所以难以提高制造半导体器件的吞吐量。 在本发明中，在单层抗蚀剂图案上沉积氧化硅膜或氮化硅膜。 使用氧化硅膜或氮化硅膜形成对应于栅极支脚的虚拟图案。 栅电极的一条腿形成在虚拟图案的部分。 根据本发明，不需要提高分辨率的步骤，并且可以通过调节氮化硅膜的厚度来获得具有几百安培的极细线宽的栅电极。

公开(公告)号：US5885847A

公开(公告)日：1999-03-23

申请号：US835957

申请日：1997-04-11

Applicant: Hyung-Sup Yoon ,  Jin-Hee Lee ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

Inventor： Hyung-Sup Yoon ,  Jin-Hee Lee ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC: H01L29/778 ,  H01L21/20 ,  H01L21/205 ,  H01L27/144 ,  H01L21/00 ,  H01L21/338

CPC classification number: H01L27/1443

Abstract: The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the steps of sequentially forming a plurality of first epitaxial layers for manufacturing the first compound semiconductor device on the semiconductor substrate; forming a first insulating film pattern for defining an active region of the first compound semiconductor device; etching the plurality of first epitaxial layers using the first insulating film pattern as a mask; forming a second insulating film on the resultant structure; forming a sidewall insulating spacer on the sidewall of the active region of the first compound semiconductor device by dry etching the second insulating film; sequentially forming a plurality of second epitaxial layers for manufacturing the second compound semiconductor device on the portion from which the plurality of first epitaxial layers is etched back; forming each electrode of the first and second compound semiconductor devices; and forming an interconnection electrode interconnecting each electrode of the first and second compound semiconductor devices.

Abstract translation: 本发明涉及通过在公共半导体衬底上形成具有多个不同外延层的第一和第二化合物半导体器件来制造化合物半导体器件的方法。 该方法包括以下步骤：在半导体衬底上依次形成用于制造第一化合物半导体器件的多个第一外延层; 形成用于限定所述第一化合物半导体器件的有源区的第一绝缘膜图案; 使用第一绝缘膜图案作为掩模蚀刻多个第一外延层; 在所得结构上形成第二绝缘膜; 通过干蚀刻所述第二绝缘膜，在所述第一化合物半导体器件的有源区的侧壁上形成侧壁绝缘间隔物; 在多个第一外延层被回蚀的部分上依次形成用于制造第二化合物半导体器件的多个第二外延层; 形成第一和第二化合物半导体器件的每个电极; 以及形成互连所述第一和第二化合物半导体器件的每个电极的互连电极。

公开(公告)号：US5856232A

公开(公告)日：1999-01-05

申请号：US675972

申请日：1996-07-05

Applicant: Jeon-Wook Yang ,  Eung-Gee Oh ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

Inventor： Jeon-Wook Yang ,  Eung-Gee Oh ,  Byung-Sun Park ,  Chul-Sun Park ,  Kwang-Eui Pyun

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L29/41 ,  H01L29/812

CPC classification number: H01L21/28587 ,  H01L21/28581 ,  Y10S148/10

Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Abstract translation: 一种制造T形栅电极的方法包括以下步骤：在半导体衬底上形成精细栅极图案; 在其上形成有栅极图案的半导体衬底上形成绝缘层，并在绝缘层上形成平坦化层以使半导体衬底的表面平坦化; 蚀刻平坦化层以暴露绝缘层的顶部; 使用平坦化层作为掩模，各向同性蚀刻绝缘层以露出栅极图案; 蚀刻暴露的栅极图案以选择性地暴露半导体衬底; 沉积栅极金属以覆盖暴露的基板，绝缘层和平坦化层，以形成T形门; 同时除去平坦化层，从而形成T形门金属，生产率提高。

公开(公告)号：US5798277A

公开(公告)日：1998-08-25

申请号：US729841

申请日：1996-10-15

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/0821 ,  H01L29/7371 ,  Y10S148/05 ,  Y10S148/072

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.

Abstract translation: 一种用于制造异质结双极晶体管的改进方法，其包括以下步骤：在半导体衬底上形成掩埋集电极，集电极薄膜和集电极沉降片，以形成第一氧化硅膜，基极多晶硅层，氮化物 在所得到的基板上暴露第一硅氧化膜的氧化膜，在暴露区域的侧面形成间隔绝缘膜，并限定激活区域，使用掩模曝光激活区域的集电极薄膜， 并形成用于隔离器件的辅助横向膜，通过将离子注入到由辅助侧膜限制的活化区域的掺杂剂形成选择性集电极区域，去除辅助横向膜，在各向异性层中蚀刻暴露部分 蚀刻方法，以及形成用于器件隔离的浅沟槽，形成多晶硅侧膜以具有s的高度 ame作为浅沟槽上的基极多晶硅层的高度，并形成自对准基底。

公开(公告)号：US06614086B2

公开(公告)日：2003-09-02

申请号：US09927312

申请日：2001-08-13

Applicant: Gyung Ock Kim ,  In Kyu Kim ,  Kwang Eui Pyun

Inventor： Gyung Ock Kim ,  In Kyu Kim ,  Kwang Eui Pyun

IPC: H01L31107

CPC classification number: B82Y20/00 ,  H01L27/15 ,  H01L31/02165 ,  H01L31/035236 ,  H01L31/107

Abstract: There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.

公开(公告)号：US06392781B1

公开(公告)日：2002-05-21

申请号：US09498610

申请日：2000-02-04

Applicant: Je Ha Kim ,  Chan Yong Park ,  Kwang Eui Pyun

Inventor： Je Ha Kim ,  Chan Yong Park ,  Kwang Eui Pyun

IPC: G02F103

CPC classification number: B82Y20/00 ,  G02F1/01708

Abstract: The present invention relates to an electrical field absorbing semiconductor optical modulator, more particularly, to a high speed semiconductor optical modulator and a fabricating method thereof. The present invention includes a high speed semiconductor optical modulator, the optical modulator formed by stacking an n-type light-wave guiding layer, a light absorbing layer, a p-type light-wave guiding layer, a p-type clad layer, and a p-type ohmic contact layer on a substrate successively, the optical modulator having a ridge structure wherein the optical modulator is an electric-field absorbing type, and wherein width W3 of the light absorbing layer is less than the width W1 of the p-type ohmic contact layer. Accordingly, the present invention enables to provide high speed optical modulation of tens of giga rate of which modulating characteristics are excellent by reducing contact resistance and capacitance, which are the major problems of ruining the characteristics of an optical modulator, simultaneously.

Abstract translation: 本发明涉及一种电场吸收半导体光调制器，更具体地涉及一种高速半导体光调制器及其制造方法。 本发明包括高速半导体光调制器，通过堆叠n型光波导层，光吸收层，p型光波导层，p型覆层和 基板上的p型欧姆接触层，其光调制器具有脊结构，其中光调制器是电场吸收型，并且其中光吸收层的宽度W3小于p型欧姆接触层的宽度W1， 型欧姆接触层。 因此，本发明能够通过降低接触电阻和电容来提供几十兆比特的高速光调制，其中调制特性同时是破坏光调制器特性的主要问题。

公开(公告)号：US5989961A

公开(公告)日：1999-11-23

申请号：US116904

申请日：1998-07-17

Applicant: Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

Inventor： Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC: H01L29/78 ,  H01L21/338 ,  H01L29/812 ,  H01L21/336

CPC classification number: H01L29/66856 ,  H01L29/812

Abstract: Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.

Abstract translation: 公开了用于制造垂直沟道晶体管的方法，包括以下步骤：选择性地将高浓度的掺杂剂注入到半导体衬底中以形成源极区; 首先使用绝缘体和第一光致抗蚀剂图案作为掩模蚀刻半导体衬底; 其次使用具有对应于所述源区域的形状的第二光致抗蚀剂图案作为掩模蚀刻所述基板; 使用所述第二光致抗蚀剂图案作为掩模将低浓度的掺杂剂注入暴露的衬底中以形成垂直沟道层; 使用相同的掩模将高浓度的掺杂剂注入暴露的衬底中以形成漏区; 激活所述掺杂剂，并在所述漏极区上形成欧姆接触层; 第三次使用第三光致抗蚀剂图案进行蚀刻，以将基板的第一蚀刻部分暴露为掩模; 在通过第三次蚀刻暴露的衬底上沉积栅极金属; 并分别接线金属。 本发明可以容易地制造具有低寄生电阻和非常小的栅极长度的垂直沟道晶体管，而无需复杂的复杂工艺。