公开(公告)号：US08172140B2

公开(公告)日：2012-05-08

申请号：US12181401

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G06K7/08

CPC classification number: G06F21/87

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract translation: 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。

公开(公告)号：US07884625B2

公开(公告)日：2011-02-08

申请号：US12181365

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

IPC: G01R27/26

CPC classification number: H01L23/576 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2224/0401

Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically include metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract translation: 装置，方法和程序产品可以通过检测与微芯片的背面附近的电容结构相关联的测量电容中的不可接受的改变来检测试图篡改微芯片。 电容结构通常包括金属形状，并且可以使用硅硅通孔连接到微芯片内的主动感测电路。 响应于感测到的变化，可以启动关机，欺骗，自毁或其他防御动作以保护微芯片的安全敏感电路。

公开(公告)号：US20100026506A1

公开(公告)日：2010-02-04

申请号：US12181342

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G08B21/00

CPC classification number: G06F21/86 ,  H01L23/576 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/16251 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action.

Abstract translation: 一种装置和方法，通过包括包括保护盖的电容电路来检测微芯片篡改。 电介质材料可以夹在盖子和背面金属层之间，背面金属层可以靠近微芯片的受保护表面。 可以感测到由电容电路的盖或其他部件的改变引起的上述电路的电容的变化，并且具有迅速的防御作用。

公开(公告)号：US20100026326A1

公开(公告)日：2010-02-04

申请号：US12181387

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G01R27/08

CPC classification number: G06F21/755 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract translation: 一种方法，程序产品和装置包括位于安全敏感的微芯片电路附近的电阻结构。 可以检测抵抗结构的位置，构成或布置的变化，并启动防止逆向工程或其他开发工作的动作。 电阻结构可以被自动和选择性地指定用于监测。 一些电阻结构可能具有不同的电阻率。 感测的电阻可以与期望的电阻，比率或其他电阻相关值进行比较。 结构可能与假结构混合，并且可以相对于彼此重叠或以其它方式布置，以进一步使不受欢迎的分析复杂化。

公开(公告)号：US20090055134A1

公开(公告)日：2009-02-26

申请号：US11844861

申请日：2007-08-24

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Trevor J. Timpane

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Trevor J. Timpane

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/40

Abstract: System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package.

Abstract translation: 用于设计电子封装的系统和方法。 布置管理员从包装设计工具接收电子包装的物理设计。 放置管理器接收关于电子封装的物理设计的设计约束。 布置管理器在电子封装的物理设计中插入用于至少一个除气开口的规格，其中根据关于所述电子封装的所述物理设计的所述设计约束创建至少一个除气开口的规格。 布局管理器输出电子包的更新的物理设计。

公开(公告)号：US20080151658A1

公开(公告)日：2008-06-26

申请号：US12034773

申请日：2008-02-21

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C7/10

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储电路包括低速输入路径和通过输入耦合耦合到其的高速输入路径并形成公共输入，公共输入耦合到存储器 存储器核具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。

公开(公告)号：US09003559B2

公开(公告)日：2015-04-07

申请号：US12181357

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

IPC: G06F1/26 ,  G06F11/00 ,  G08B13/00 ,  G08B21/00 ,  G08B29/00 ,  G06F21/87

CPC classification number: G06F21/87

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract translation: 装置，方法和程序产品通过确定包括一个或多个连接的电路径和连接到微芯片的背面的金属板已经断开或以其他方式改变来检测试图篡改微芯片。 响应于不可能存在的电路径的存在，也可以检测到篡改尝试，这可能是因为微芯片被错误地重新构成。 可以自动选择和监视实际和/或欺骗性路径，以进一步混淆反向工程尝试。

公开(公告)号：US07701244B2

公开(公告)日：2010-04-20

申请号：US12181367

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

IPC: H03K19/00

CPC classification number: G06F21/86 ,  G06F21/75 ,  H01L23/57 ,  H01L2224/32225

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract translation: 检测微芯片篡改的集成电路组件和相关联的方法可以包括与导电层电连通的多个连接。 防御性电路可能会阻止微芯片的分析，其中连接不再连接到导电层。 防御性电路可以类似地启动，其中连接不想与导电层电连通的连接是连接的。

公开(公告)号：US07667487B2

公开(公告)日：2010-02-23

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/173

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。

公开(公告)号：US20090179669A1

公开(公告)日：2009-07-16

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/0175 ,  G06F1/26

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。