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    SRAM array with dynamic voltage for reducing active leakage power
    14.
    发明授权
    SRAM array with dynamic voltage for reducing active leakage power 有权
    具有动态电压的SRAM阵列，用于降低有源漏电功率

    公开(公告)号：US06724648B2

    公开(公告)日：2004-04-20

    申请号：US10117163

    申请日：2002-04-05

    Applicant: Muhammad Khellah ,  Vivek De ,  Dinesh Somasekhar ,  Yibin Ye

    Inventor： Muhammad Khellah ,  Vivek De ,  Dinesh Somasekhar ,  Yibin Ye

    IPC: G11C1140

    CPC classification number: G11C11/417

    Abstract: A power management device and static random access memory (SRAM) architecture with dynamic supply voltages reduce active power leakage in SRAM cells. When a cell is inactive, a low level supply voltage is applied to the source line connected to the cell to maintain the data stored in the cell. However, before a cell is accessed (e.g., during a read or write operation), the source line is raised to a high level supply voltage.

    Abstract translation: 具有动态电源电压的电源管理器件和静态随机存取存储器（SRAM）架构降低了SRAM单元中的有功功率泄漏。 当单元不活动时，低电平电源电压被施加到连接到单元的源极线以维持存储在单元中的数据。 然而，在单元被访问之前（例如，在读取或写入操作期间），源极线被升高到高电平电源电压。

    Register file circuits with P-type evaluation
    17.
    发明申请
    Register file circuits with P-type evaluation 有权
    注册文件电路与P型评估

    公开(公告)号：US20100157705A1

    公开(公告)日：2010-06-24

    申请号：US12317000

    申请日：2008-12-18

    Applicant: Bibiche Geuskens ,  Ataur Patwary ,  Eric Kwesi Donkoh ,  Muhammad Khellah ,  Tanay Karnik

    Inventor： Bibiche Geuskens ,  Ataur Patwary ,  Eric Kwesi Donkoh ,  Muhammad Khellah ,  Tanay Karnik

    IPC: G11C7/00

    CPC classification number: G11C7/12 ,  G11C7/22 ,  G11C2207/007 ,  H03K19/01742

    Abstract: Provided herein is a new RF implementation. Instead of using a pre-charged High node for one or more of its evaluation nodes, it employs an evaluation (or evaluate) node that is discharged (Low) prior to evaluation and enters evaluation in a discharged state. In some embodiments, with such “normally Low” evaluation nodes, it uses pull-up stack devices, rather than pull-down devices, to charge the evaluate node during an evaluate phase if the logic so dictates.

    Abstract translation: 这里提供了一种新的RF实现。 不是为其一个或多个评估节点使用预充电的高节点，而是在评估之前使用放电（低）的评估（或评估）节点，并在放电状态下进行评估。 在一些实施例中，利用这种“通常为低”的评估节点，如果逻辑如此指示，则使用上拉堆栈设备而不是下拉设备在评估阶段期间对评估节点充电。

    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY
    18.
    发明申请
    APPARATUS AND METHOD FOR PROGRAMMING A MEMORY ARRAY 失效
    用于编程存储阵列的装置和方法

    公开(公告)号：US20060285393A1

    公开(公告)日：2006-12-21

    申请号：US11158518

    申请日：2005-06-21

    Applicant: Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    Inventor： Fabrice Paillet ,  Ali Keshavarzi ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Stephen Tang ,  Mohsen Alavi ,  Vivek De ,  Tanay Karnik

    IPC: G11C16/04

    CPC classification number: G11C17/18

    Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

    Abstract translation: 提供了一种对存储器阵列进行编程的方法，包括通过相对于各个字线相互依次提供多个电压步骤来访问存储器阵列的多个字线，以及每个存储器阵列的多个位线 访问相应字线的时间，对与同时访问的各个字和位线相对应的多个设备进行编程，每个设备通过断开设备的介电层进行编程，访问位线被排序，使得只有 一个设备中的单个设备一次被编程。

    Purge-based floating body memory
    19.
    发明申请
    Purge-based floating body memory 有权
    基于清洗的浮体记忆

    公开(公告)号：US20060279985A1

    公开(公告)日：2006-12-14

    申请号：US11151982

    申请日：2005-06-14

    Applicant: Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

    Inventor： Ali Keshavarzi ,  Stephen Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad Khellah ,  Yibin Ye ,  Vivek De ,  Gerhard Schrom

    IPC: G11C11/34

    CPC classification number: G11C11/404 ,  G11C2211/4016

    Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

    Abstract translation: 通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。 每个存储单元包括具有能够存储电荷的浮动体的晶体管。 多个字线和清除线与存储器单元的行互连。 多个位线被连接到存储器单元的列。 通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

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