公开(公告)号：US20130059422A1

公开(公告)日：2013-03-07

申请号：US13599844

申请日：2012-08-30

Applicant: Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

Inventor： Bo-Young LEE ,  Jongwan CHOI ,  Myoungbum LEE

IPC: H01L21/764 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

公开(公告)号：US08173533B2

公开(公告)日：2012-05-08

申请号：US13299855

申请日：2011-11-18

Applicant: Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H01L21/4763 ,  H01L27/01

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

Abstract translation: 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

公开(公告)号：US20100163968A1

公开(公告)日：2010-07-01

申请号：US12650137

申请日：2009-12-30

Applicant: Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

Abstract translation: 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

公开(公告)号：US20160111440A1

公开(公告)日：2016-04-21

申请号：US14973182

申请日：2015-12-17

Applicant: Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/115 ,  H01L29/40 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱，多个栅电极和多个支撑体。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极与活性柱相交，从存储单元区延伸到接触区，并且堆叠在半导体衬底上。 支撑体在接触区域中垂直于半导体衬底延伸以穿透至少一个或多个栅电极。

公开(公告)号：US09196630B2

公开(公告)日：2015-11-24

申请号：US14519821

申请日：2014-10-21

Applicant: Bo-Young Lee ,  Jongwan Choi ,  Myoungbum Lee

Inventor： Bo-Young Lee ,  Jongwan Choi ,  Myoungbum Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/764 ,  H01L21/762 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/76229 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.

Abstract translation: 半导体器件及其制造方法包括在彼此相邻的衬底上的多个图案之间形成沟槽，在沟槽中形成第一牺牲层，形成具有多个孔的第一多孔绝缘层 所述多个图案和所述第一牺牲层上，并且通过所述第一多孔绝缘层的所述多个孔去除所述第一牺牲层，以在所述多个图案之间和所述第一多孔绝缘层下方形成第一气隙。

公开(公告)号：US20150249093A1

公开(公告)日：2015-09-03

申请号：US14574456

申请日：2014-12-18

Applicant: Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

Inventor： Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

IPC: H01L27/115

CPC classification number: H01L27/11582

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

Abstract translation: 提供了一种半导体器件，其包括在衬底上的栅极结构，栅极结构平行于第一方向延伸并且通过插入其间的分离沟槽彼此间隔开，每个栅极结构包括堆叠在衬底上的绝缘图案， 栅电极插入其间; 通过栅极结构连接到衬底的垂直柱; 隔离沟槽中的绝缘间隔物覆盖每个栅极结构的侧壁; 以及在栅电极和绝缘间隔物之间​​的扩散阻挡结构。

公开(公告)号：US20130228843A1

公开(公告)日：2013-09-05

申请号：US13761327

申请日：2013-02-07

Applicant: Tai-Soo LIM ,  Kihyun YUN ,  Jeonggil LEE ,  HyunSeok LIM ,  HAUK HAN ,  MYOUNGBUM LEE

Inventor： Tai-Soo LIM ,  Kihyun YUN ,  Jeonggil LEE ,  HyunSeok LIM ,  HAUK HAN ,  MYOUNGBUM LEE

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/788 ,  H01L27/11529 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer.

Abstract translation: 非易失性存储器件包括衬底上的存储器栅极图案和衬底上的非存储器栅极图案，非存储器栅极图案与存储器栅极图案间隔开，其中非存储器栅极图案包括欧姆层 并且提供存储器栅极图案而没有欧姆层。

公开(公告)号：US08084819B2

公开(公告)日：2011-12-27

申请号：US12650137

申请日：2009-12-30

Applicant: Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

Inventor： Jingyun Kim ,  Myoungbum Lee ,  Kihyun Hwang

IPC: H01L27/01 ,  H01L21/4763

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

Abstract translation: 提供半导体存储器件和形成半导体存储器件的方法。 所述方法可以包括形成交替层叠在基板上的绝缘层和单元栅极层，通过连续图案化通过单元栅极层和绝缘层形成开口，并且在开口中的单元栅极层的侧壁上选择性地形成导电阻挡层 。

公开(公告)号：US20110101443A1

公开(公告)日：2011-05-05

申请号：US12894615

申请日：2010-09-30

Applicant: ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

Inventor： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

IPC: H01L29/792

CPC classification number: H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

Abstract: Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

Abstract translation: 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 层叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

公开(公告)号：US20100133599A1

公开(公告)日：2010-06-03

申请号：US12592869

申请日：2009-12-03

Applicant: Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L29/788

CPC classification number: H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱，多个栅电极和多个支撑体。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极与活性柱相交，从存储单元区延伸到接触区，并且堆叠在半导体衬底上。 支撑体在接触区域中垂直于半导体衬底延伸以穿透至少一个或多个栅电极。