公开(公告)号：US20110101443A1

公开(公告)日：2011-05-05

申请号：US12894615

申请日：2010-09-30

申请人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

发明人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 层叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

公开(公告)号：US20130005104A1

公开(公告)日：2013-01-03

申请号：US13615890

申请日：2012-09-14

申请人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

发明人： ZongLiang HUO ,  Myoungbum LEE ,  Kihyun HWANG ,  Seungmok SHIN ,  Sunjung KIM

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  H01L29/7926

摘要： Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 非易失性存储器件可以包括堆叠结构，半导体图案，信息存储层和固定电荷层。 堆叠结构可以设置在半导体衬底上。 层叠结构可以包括交替堆叠在其中的导电图案和层间电介质图案。 半导体图案可以通过层叠结构连接到半导体衬底。 信息存储层可以设置在半导体图案和导电图案之间。 固定电荷层可以设置在半导体图案和层间电介质图案之间。 固定电荷层可以包括固定电荷。 固定电荷的电极性可以等于半导体图案的多数载流子的电极性。

公开(公告)号：US20140063890A1

公开(公告)日：2014-03-06

申请号：US14018885

申请日：2013-09-05

申请人： Wookhyoung LEE ,  Jongsik CHUN ,  Sunil SHIM ,  Jaeyoung AHN ,  Juyul LEE ,  Kihyun HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Jaehoon JANG ,  Wonseok CHO

发明人： Wookhyoung LEE ,  Jongsik CHUN ,  Sunil SHIM ,  Jaeyoung AHN ,  Juyul LEE ,  Kihyun HWANG ,  Hansoo KIM ,  Woonkyung LEE ,  Jaehoon JANG ,  Wonseok CHO

IPC分类号： G11C5/06 ,  H01L23/48 ,  G11C7/00

CPC分类号： H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

摘要翻译： 提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。 每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

公开(公告)号：US20120032250A1

公开(公告)日：2012-02-09

申请号：US13182269

申请日：2011-07-13

申请人： Yong-Hoon SON ,  Sung-Min HWANG ,  Kihyun HWANG ,  Jaehoon JANG

发明人： Yong-Hoon SON ,  Sung-Min HWANG ,  Kihyun HWANG ,  Jaehoon JANG

IPC分类号： H01L29/792

CPC分类号： H01L21/76254 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

摘要： A semiconductor device can include a first substrate and conductive patterns on the first substrate, where the conductive patterns are disposed in stacks vertically extending from the substrate. An active pillar can be on the first substrate vertically extend from the first substrate through the conductive patterns to provide vertical string transistors on the first substrate. A second substrate can be on the conductive patterns and the active pillar opposite the first substrate. A peripheral circuit transistor can be on the second substrate opposite the first substrate, where the peripheral circuit transistor can be adjacent to and overlap an uppermost pattern of the conductive patterns.

摘要翻译： 半导体器件可以包括第一衬底和第一衬底上的导电图案，其中导电图案布置在从衬底垂直延伸的堆叠中。 活性柱可以在第一衬底上，从第一衬底经由导电图案垂直延伸，以在第一衬底上提供垂直串晶体管。 第二基板可以位于与第一基板相对的导电图案和有源柱上。 外围电路晶体管可以在与第一衬底相对的第二衬底上，其中外围电路晶体管可以与导电图案的最上面的图案相邻并且与其重叠。

公开(公告)号：US20170287929A1

公开(公告)日：2017-10-05

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

发明人： Sunggil KIM ,  Phil Ouk NAM ,  Gukhyon YON ,  Sunghae LEE ,  Woojin JANG ,  Dongchul YOO ,  Hunhyeong LIM ,  Junggeun JEE ,  Kihyun HWANG

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L21/0206 ,  H01L21/31116 ,  H01L27/115 ,  H01L27/1157 ,  H01L28/00 ,  H01L29/1037 ,  H01L29/40117

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20170162578A1

公开(公告)日：2017-06-08

申请号：US15302032

申请日：2014-06-23

申请人： Jintae NOH ,  Bio KIM ,  Su-Jin SHIN ,  Hanvit YANG ,  Kihyun HWANG

发明人： Jintae NOH ,  Bio KIM ,  Su-Jin SHIN ,  Hanvit YANG ,  Kihyun HWANG

IPC分类号： H01L27/105 ,  H01L29/40 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

CPC分类号： H01L27/1052 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32105 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/7926

摘要： The inventive concepts provide methods of manufacturing a semiconductor device. The method includes forming a thin layer structure including insulating layers and sacrificial layers alternately and repeatedly stacked on a substrate, forming a through-hole penetrating the thin layer structure and exposing the substrate, forming a semiconductor layer covering an inner sidewall of the through-hole and partially filling the through-hole, oxidizing a first portion of the semiconductor layer to form a first insulating layer, and injecting oxygen atoms into a second portion of the semiconductor layer. An oxygen atomic concentration of the second portion is lower than that of the first insulating layer. Oxidizing the first portion and injecting the oxygen atoms into the second portion are performed using an oxidation process at the same time.

公开(公告)号：US20150348982A1

公开(公告)日：2015-12-03

申请号：US14819841

申请日：2015-08-06

申请人： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

发明人： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L23/535

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US20130134492A1

公开(公告)日：2013-05-30

申请号：US13587379

申请日：2012-08-16

申请人： Junkyu YANG ,  Phil Ouk NAM ,  JinGyun KIM ,  Jaeyoung AHN ,  SeungHyun LIM ,  Kihyun HWANG

发明人： Junkyu YANG ,  Phil Ouk NAM ,  JinGyun KIM ,  Jaeyoung AHN ,  SeungHyun LIM ,  Kihyun HWANG

IPC分类号： H01L29/78

CPC分类号： H01L27/1157 ,  H01L27/11582

摘要： Example embodiments of inventive concepts relate to semiconductor memory devices and/or methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel penetrating the plurality of gates and a data storage layer between the vertical channel and the plurality of gates. The vertical channel may include a lower channel connected to the substrate and an upper channel on the lower channel. The upper channel may include a vertical pattern penetrating some of the plurality of gates and defining an inner space filled with an insulating layer, and a horizontal pattern horizontally extending along a top surface of the lower channel. The horizontal pattern may be in contact with the top surface of the lower channel.

摘要翻译： 本发明构思的示例性实施例涉及半导体存储器件和/或其制造方法。 半导体存储器件可以包括垂直堆叠在衬底上的多个栅极，穿过多个栅极的垂直沟道和垂直沟道与多个栅极之间的数据存储层。 垂直通道可以包括连接到基板的下通道和下通道上的上通道。 上部通道可以包括穿透多个栅极中的一些的垂直图案，并且限定填充有绝缘层的内部空间，以及沿着下部通道的顶表面水平延伸的水平图案。 水平图案可以与下通道的顶表面接触。