公开(公告)号：US20240397236A1

公开(公告)日：2024-11-28

申请号：US18322408

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Jiayu Guo ,  Liang Zuo ,  Lihang Fan

IPC: H04N25/78 ,  H04N25/616

Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

公开(公告)号：US20240397223A1

公开(公告)日：2024-11-28

申请号：US18322421

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang

IPC: H04N25/704 ,  H04N23/67 ,  H04N25/75

Abstract: An arithmetic logic unit includes a GC to binary stage, an adder stage, an adder output stage, an adder input latch stage coupled to latch outputs of the GC to binary stage, a feedback multiplexer stage coupled to receive the outputs of the GC to binary stage, a latch output multiplexer coupled to receive outputs of the first adder input latches, where the latch output multiplexer is configured to multiply the outputs of the first adder input latches by either −1 or −2, and an adder input multiplexer stage, where first inputs of the adder input multiplexer stage are coupled to receive outputs of the latch output multiplexer and second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches. The arithmetic logic performs adaptive correlated multiple sampling for image sensing pixels and phase detection auto focus for other pixels.

公开(公告)号：US20240387567A1

公开(公告)日：2024-11-21

申请号：US18318482

申请日：2023-05-16

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Chun-Yung Ai ,  Kazufumi Watanabe ,  Chih-Wei Hsiung

IPC: H01L27/146

Abstract: A pixel array substrate includes a semiconductor substrate including a pixel array, a first side, and a second side opposite the first side, a guard ring region in the semiconductor substrate, formed of a doped semiconductor, enclosing the pixel array, and extending into the semiconductor substrate from the first side, and a peripheral region in the semiconductor substrate and enclosing the guard ring region. The peripheral region includes at least one device and a deep trench isolation (DTI) structure region disposed between the guard ring region and the at least one device and proximate to the second side of the semiconductor substrate. The DTI structure region is configured to block an electric current path between a P-N junction in the guard ring region and the at least one device.

公开(公告)号：US12142625B2

公开(公告)日：2024-11-12

申请号：US17957440

申请日：2022-09-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Keiji Mabuchi

IPC: H01L27/146 ,  H01L27/148

Abstract: An imaging system including a sensor wafer and a logic wafer. The sensor wafer includes a plurality of pixels arranged in rows and columns, the plurality of pixels arranged in rows and columns and including at least a first pixel and a second pixel positioned in a first row included in the rows. The sensor wafer includes a first transfer control line associated with the first row, the first transfer control line coupled to both a first transfer gate of the first pixel and a second transfer gate of the second pixel. The logic wafer includes a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, a first storage control line coupled to a first storage gate associated with the first pixel and a second storage control line coupled to a second storage gate associated with the second pixel.

公开(公告)号：US12114092B2

公开(公告)日：2024-10-08

申请号：US18171227

申请日：2023-02-17

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang ,  Hiroaki Ebihara

IPC: H04N25/78 ,  H04N25/77

CPC classification number: H04N25/78 ,  H04N25/77

Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.

公开(公告)号：US12106599B2

公开(公告)日：2024-10-01

申请号：US17839000

申请日：2022-06-13

Applicant: OmniVision Technologies, Inc.

Inventor： Jau-Jan Deng ,  Yi-Wei Liu

IPC: G06V40/13 ,  G06F3/041 ,  G06F3/042 ,  H04M1/02

CPC classification number: G06V40/1318 ,  G06F3/0412 ,  G06F3/042 ,  H04M1/0266

Abstract: An image sensor for imaging fingerprints has multiple photodiode groups each with field of view through a microlens determined by optical characteristics of the microlens and locations of the microlens and openings of upper and lower mask layers. Many photodiode groups have fields of view outwardly splayed from a center-direct field of view. A diameter of openings of the upper mask layer distant from the group having a center-direct field of view is larger than openings of a photodiode group having a center-direct field of view. A method of matching illumination of a group of photodiodes with center-direct field of view to illumination of photodiode groups having outwardly splayed fields of view includes sizing openings in the upper mask layer of photodiode groups with outwardly splayed fields of view larger than openings in the upper mask layer associated with photodiode groups having center-direct field of view.

公开(公告)号：US20240314460A1

公开(公告)日：2024-09-19

申请号：US18393135

申请日：2023-12-21

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Amit Mittra ,  Kevin Johnson ,  Hiroaki Ebihara ,  Kenny Geng

IPC: H04N25/46 ,  H04N25/77 ,  H04N25/78

CPC classification number: H04N25/46 ,  H04N25/77 ,  H04N25/78

Abstract: A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.

公开(公告)号：US20240297851A1

公开(公告)日：2024-09-05

申请号：US18177616

申请日：2023-03-02

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Andreas Suess ,  Kevin Johnson

IPC: H04L47/431 ,  H04N7/04 ,  H04N25/47

CPC classification number: H04L47/431 ,  H04N7/04 ,  H04N25/47

Abstract: Methods for transmitting asynchronous event data via synchronous communications interfaces (and associated imaging systems) are disclosed herein. In one embodiment, an imager comprises an array of event vision pixels, and a synchronous communications transmitter configured to transmit frames of data to a synchronous communications receiver. The pixels generate event data based on activity within an external scene. The imager communicates, at a first time and to the receiver, an anticipated amount of data that will be included in a frame transmitted to the receiver at a second time. The anticipated amount of data can be based on a prediction of an amount of event data that will be generated at a future point in time for transmission to the receiver in the frame. The imager can then transmit the frame to the receiver at the second time with an amount of data corresponding to the anticipated amount of data.

公开(公告)号：US20240297191A1

公开(公告)日：2024-09-05

申请号：US18177826

申请日：2023-03-03

Applicant: OmniVision Technologies, Inc.

Inventor： Xiaodong Yang ,  Masao Sambongi ,  Chengming Liu ,  Chen Zhang

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14645

Abstract: In an embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 4×4 pixels including 12 green pixels, 2 blue pixels, and 2 red pixels, where a minimal repeating unit is immediately next to another minimal repeating unit in row and column directions. In another embodiment, an image sensor comprises a pixel array having a minimal repeating unit, where the minimal repeating unit consists of 8×8 pixels including 48 green pixels, 8 blue pixels, and 8 red pixels.

公开(公告)号：US12075179B2

公开(公告)日：2024-08-27

申请号：US18047588

申请日：2022-10-18

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Rui Wang

IPC: H04N25/772 ,  G06F7/501 ,  G06F7/57

CPC classification number: H04N25/772 ,  G06F7/501 ,  G06F7/57

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.