公开(公告)号：US5159260A

公开(公告)日：1992-10-27

申请号：US4307

申请日：1987-01-07

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185

CPC分类号： G11C11/4113 ,  G05F3/245 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45179 ,  H03F3/45744 ,  H03F3/45748 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394

摘要： This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

摘要翻译： 该参考电压发生器装置检测与半导体的能隙对应的电压或与其接近的值的电压或基于半导体的能级的电压，并产生检测电压作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同的半导体材料制成的本征半导体的两个半导体制成，并且具有费米 能量水平值彼此不同。 第一和第二IGFET的通道具有相同的导电类型。 基于自对准结构，至少第一和第二多晶半导体区域的那些部分是靠近源区和漏区的第一和第二IGFET的栅电极，其掺杂与源的相同杂质 和漏极区域，并且第一和第二多晶半导体区域之一的中心部分掺杂有选择的第一导电类型和第二导电类型的杂质。

公开(公告)号：US4020367A

公开(公告)日：1977-04-26

申请号：US687510

申请日：1976-05-18

申请人： Osamu Yamashiro ,  Shunji Shimada

发明人： Osamu Yamashiro ,  Shunji Shimada

IPC分类号： G05F3/24 ,  H02J1/04 ,  G05F1/52 ,  H03K1/12

CPC分类号： G05F3/247 ,  G05F3/245

摘要： A constant-current circuit comprising a first enhancement type FET, a depletion type FET having its drain and source connected to the drain and gate of the first enhancement type FET respectively, a second enhancement type FET having its drain and source connected to the gate and source of the first enhancement type FET and a series connection of two impedance elements having its ends connected to the source of the depletion type FET and to the source of the second enhancement type FET, the juncture between the two impedance elements being connected to the gate of the second enhancement type FET, whereby the constant-current characteristics of such constant-current circuits are checked from being dispersed.

摘要翻译： 一种恒流电路，包括第一增强型FET，耗尽型FET，其漏极和源极分别连接到第一增强型FET的漏极和栅极;第二增强型FET，其漏极和源极连接到栅极， 第一增强型FET的源极以及其端部连接到耗尽型FET的源极和第二增强型FET的源极的两个阻抗元件的串联连接，两个阻抗元件之间的接合部连接到栅极 的第二增强型FET，从而分散这些恒流电路的恒流特性。

公开(公告)号：US4559694A

公开(公告)日：1985-12-24

申请号：US484351

申请日：1983-04-12

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185 ,  H01L21/64

CPC分类号： H03F3/45179 ,  G05F3/245 ,  G11C11/4113 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45744 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394 ,  Y10S148/053 ,  Y10S148/07

摘要： A method is provided for manufacturing a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.

摘要翻译： 提供了一种用于制造基准电压发生器装置的方法，该装置检测对应于半导体的能隙的电压或接近其的值的电压或基于半导体的能级的电压，并产生检测电压 作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同半导体材料制成的本征半导体，但具有费米的两个半导体 能量水平值彼此不同。

公开(公告)号：US4039973A

公开(公告)日：1977-08-02

申请号：US677065

申请日：1976-04-15

申请人： Osamu Yamashiro

发明人： Osamu Yamashiro

IPC分类号： H03B5/32 ,  G04F5/06 ,  H03B5/36 ,  H03K3/354 ,  H03L3/00

CPC分类号： H03L3/00 ,  G04F5/06 ,  H03K3/3545

摘要： In a crystal-controlled oscillator circuit comprising a complementary-MOS inverter provided with a crystal in the feed-back circuit, an initiation circuit is provided which comprises another complementary-MOS inverter connected in parallel to said MOS inverter only at the time of initiation. This oscillator circuit includes a parallel circuit connection of two complementary MOS inverters at the time of initiation and hence has a large driving power and a short oscillation initiation time. Because of rendering one complementary MOS inverter to be cut off at the time of normal oscillation, the power consumption is reduced.

公开(公告)号：US5481484A

公开(公告)日：1996-01-02

申请号：US953533

申请日：1992-09-28

申请人： Munehiro Ogawa, deceased ,  Masato Iwabuchi ,  Hitoshi Sugihara ,  Saburo Hojo ,  Masami Kinoshita ,  Osamu Yamashiro ,  Goichi Yokomizo ,  Mikako Miyama

发明人： Munehiro Ogawa, deceased ,  Masato Iwabuchi ,  Hitoshi Sugihara ,  Saburo Hojo ,  Masami Kinoshita ,  Osamu Yamashiro ,  Goichi Yokomizo ,  Mikako Miyama

IPC分类号： G06F11/25 ,  G01R31/3167 ,  G06F17/50 ,  G06J1/00

CPC分类号： G06F17/5022 ,  G01R31/3167 ,  G06F17/5036

摘要： A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

摘要翻译： 考虑到对模拟分析电路部分的影响，提供混合模式模拟方法和装置，用于高精度地模拟数字分析电路部分和模拟分析电路部分的总体特性，它们都经过混合模式模拟 由数字分析电路部分消耗的电流。 更具体地，与逻辑模拟同步地确定由模拟分析电路部分提供由于由逻辑模拟实现的数字分析电路部分的操作状态而产生的电流的电流计算的等效电路的电流值，并且 由此得到的电流计算的等效电路由模拟分析电路部分组成，该复合电路进行电路仿真。

公开(公告)号：USRE31749E

公开(公告)日：1984-11-27

申请号：US168777

申请日：1980-07-11

申请人： Osamu Yamashiro

发明人： Osamu Yamashiro

IPC分类号： G04F5/06 ,  H01L21/822 ,  H01L27/04 ,  H03B5/36 ,  H03F3/20 ,  H03F3/213 ,  H03F3/30 ,  H03F3/34 ,  H03F3/345 ,  H03F3/347 ,  H03K19/0948

CPC分类号： G04F5/06 ,  H03F3/3028 ,  H03K19/0948

摘要： A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.