公开(公告)号：US5159260A

公开(公告)日：1992-10-27

申请号：US4307

申请日：1987-01-07

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185

CPC分类号： G11C11/4113 ,  G05F3/245 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45179 ,  H03F3/45744 ,  H03F3/45748 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394

摘要： This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

摘要翻译： 该参考电压发生器装置检测与半导体的能隙对应的电压或与其接近的值的电压或基于半导体的能级的电压，并产生检测电压作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同的半导体材料制成的本征半导体的两个半导体制成，并且具有费米 能量水平值彼此不同。 第一和第二IGFET的通道具有相同的导电类型。 基于自对准结构，至少第一和第二多晶半导体区域的那些部分是靠近源区和漏区的第一和第二IGFET的栅电极，其掺杂与源的相同杂质 和漏极区域，并且第一和第二多晶半导体区域之一的中心部分掺杂有选择的第一导电类型和第二导电类型的杂质。

公开(公告)号：US4559694A

公开(公告)日：1985-12-24

申请号：US484351

申请日：1983-04-12

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185 ,  H01L21/64

CPC分类号： H03F3/45179 ,  G05F3/245 ,  G11C11/4113 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45744 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394 ,  Y10S148/053 ,  Y10S148/07

摘要： A method is provided for manufacturing a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.

摘要翻译： 提供了一种用于制造基准电压发生器装置的方法，该装置检测对应于半导体的能隙的电压或接近其的值的电压或基于半导体的能级的电压，并产生检测电压 作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同半导体材料制成的本征半导体，但具有费米的两个半导体 能量水平值彼此不同。

公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

摘要翻译： 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5189497A

公开(公告)日：1993-02-23

申请号：US765065

申请日：1991-09-24

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/105 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US5122857A

公开(公告)日：1992-06-16

申请号：US638768

申请日：1991-01-08

申请人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC分类号： H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US4792841A

公开(公告)日：1988-12-20

申请号：US634037

申请日：1984-07-24

申请人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

发明人： Kouichi Nagasawa ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Satoshi Meguro

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8244 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11 ,  H01L29/04

CPC分类号： H01L27/1112 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.

摘要翻译： 公开了包括多个硅栅型MOSFET的MOSIC，其中在与多晶硅栅极同时形成多晶硅布线之后，与源极和漏极区域接触的电极由多晶硅制成，以便连接到多晶硅 从而防止源极和漏极区域的浅的pn结被触点破坏并提供与一个硅芯片的高度集成。

公开(公告)号：US4734383A

公开(公告)日：1988-03-29

申请号：US800954

申请日：1985-11-22

申请人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L29/0847 ,  H01L27/0928

摘要： After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

摘要翻译： 在P和N沟道MOSFET的P型和N型源极区或漏极区的接触孔已经制成了共同的步骤之后，N型杂质被离子注入至少N型源极或漏极 区域通过接触孔。 将N型杂质退火，形成比N型源区或漏区更深的N型区。 在退火处理期间，N型源极或漏极区域被绝缘膜覆盖。

公开(公告)号：US20060014347A1

公开(公告)日：2006-01-19

申请号：US11220723

申请日：2005-09-08

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

公开(公告)号：US5700704A

公开(公告)日：1997-12-23

申请号：US458615

申请日：1995-06-02

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

摘要翻译： 提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。 特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻 的多晶硅膜。 通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。