公开(公告)号：US20240312831A1

公开(公告)日：2024-09-19

申请号：US18566474

申请日：2022-05-25

Applicant: SOITEC ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Alexis Drouin ,  Gweltaz Gaudin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Julie Widiez ,  Emmanuel Rolland

IPC: H01L21/762 ,  H01L21/04

CPC classification number: H01L21/76254 ,  H01L21/0445

Abstract: A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.

公开(公告)号：US20240290615A1

公开(公告)日：2024-08-29

申请号：US18647252

申请日：2024-04-26

Applicant: Soitec

Inventor： Young-Pil Kim

IPC: H01L21/02 ,  C23C16/24 ,  C23C16/26 ,  C23C16/44

CPC classification number: H01L21/02658 ,  C23C16/24 ,  C23C16/26 ,  C23C16/4404 ,  C23C16/4405 ,  H01L21/02238

Abstract: A support for a semiconductor structure comprises a base substrate and a charge trapping layer on the base substrate. The charge trapping layer comprises an alternating stack of at least one polycrystalline charge trapping material and at least one polycrystalline interlayer. The charge trapping material has a grain size between 100 nanometers (nm) and 1000 nm, and/or a lattice parameter greater than a lattice parameter of the at least one interlayer. Also disclosed is a semiconductor structure comprising such support.

公开(公告)号：US12074056B2

公开(公告)日：2024-08-27

申请号：US18047113

申请日：2022-10-17

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/84 ,  H01L27/1207 ,  H01L21/02532

Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US20240170284A1

公开(公告)日：2024-05-23

申请号：US18550044

申请日：2022-03-03

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Christophe Maleville ,  lonut Radu ,  Hugo Biard

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/762

CPC classification number: H01L21/02529 ,  C23C16/0227 ,  C23C16/325 ,  C23C16/56 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/76254

Abstract: A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.

公开(公告)号：US11979132B2

公开(公告)日：2024-05-07

申请号：US17042016

申请日：2019-03-27

Applicant: Soitec

Inventor： Djamel Belhachemi ,  Thierry Barge

IPC: H03H3/02 ,  H10N30/00 ,  H10N30/05 ,  H10N30/073 ,  H10N30/853

CPC classification number: H03H3/02 ,  H10N30/05 ,  H10N30/073 ,  H10N30/10516 ,  H10N30/8542 ,  Y10T29/42

Abstract: A method for manufacturing a substrate for a radiofrequency filter by joining a piezoelectric layer to a carrier substrate via an electrically insulating layer, wherein the method comprises depositing the electrically insulating layer by spin coating an oxide belonging to the family of SOGs (spin-on glasses) on the surface of the piezoelectric layer to be joined to the carrier substrate, followed by an anneal for densifying the electrically insulating layer before joining the piezoelectric layer to the carrier substrate via the electrically insulating layer.

公开(公告)号：US20240146275A1

公开(公告)日：2024-05-02

申请号：US18404685

申请日：2024-01-04

Applicant: Soitec

Inventor： Djamel Belhachemi ,  Thierry Barge

IPC: H03H3/10 ,  C09J7/30 ,  H03H9/02 ,  H03H9/25 ,  H03H9/64 ,  H10N30/073 ,  H10N30/08 ,  H10N30/082 ,  H10N30/086

CPC classification number: H03H3/10 ,  C09J7/30 ,  H03H9/02574 ,  H03H9/02834 ,  H03H9/02897 ,  H03H9/25 ,  H03H9/6489 ,  H10N30/073 ,  H10N30/08 ,  H10N30/082 ,  H10N30/086

Abstract: A process for fabricating a substrate for a radiofrequency device includes providing a piezoelectric substrate and a carrier substrate, depositing a dielectric layer on a surface of the piezoelectric substrate, assembling together the piezoelectric substrate and the carrier substrate with a polymerizable adhesive directly between the dielectric layer and the carrier substrate to form an assembled substrate, and polymerizing the polymerizable adhesive layer to form a polymerized layer bonding the piezoelectric substrate to the carrier substrate, the polymerized layer and the dielectric layer together forming an electrically insulating layer between the piezoelectric substrate and the carrier substrate,

公开(公告)号：US20240145314A1

公开(公告)日：2024-05-02

申请号：US18402215

申请日：2024-01-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11974505B2

公开(公告)日：2024-04-30

申请号：US17044132

申请日：2019-03-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Christelle Veytizou

IPC: H03H9/02 ,  H03H3/10 ,  H10N30/00 ,  H10N30/079 ,  H10N30/097

CPC classification number: H10N30/10516 ,  H03H3/10 ,  H03H9/02559 ,  H03H9/02574 ,  H03H9/02834 ,  H10N30/079 ,  H10N30/097

Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.

公开(公告)号：US11935743B2

公开(公告)日：2024-03-19

申请号：US17042728

申请日：2019-03-26

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: H01L21/02 ,  C30B23/02 ,  C30B25/18 ,  C30B29/04 ,  C30B29/06

CPC classification number: H01L21/02293 ,  C30B23/025 ,  C30B25/183 ,  C30B29/04 ,  C30B29/06

Abstract: A process for producing a monocrystalline layer of diamond or iridium material comprises transferring a monocrystalline seed layer of SrTiO3 material onto a carrier substrate of silicon material, followed by epitaxial growth of the monocrystalline layer of diamond or iridium material.

公开(公告)号：US20230411205A1

公开(公告)日：2023-12-21

申请号：US18451486

申请日：2023-08-17

Applicant: Soitec

Inventor： Didier Landru ,  Bruno Ghyselen

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/78

CPC classification number: H01L21/76254 ,  H01L21/7813 ,  H01L21/26506

Abstract: A process for transferring blocks from a donor to a receiver substrate, comprises: arranging a mask facing a free surface of the donor substrate, the mask having one or more openings that expose the free surface of the donor substrate, the openings distributed according to a given pattern; forming, by ion implantation through the mask, an embrittlement plane in the donor substrate vertically in line with at least one region exposed through the mask, the embrittlement plane delimiting a respective surface region; forming a block that is raised relative to the free surface of the donor substrate localized vertically in line with each respective embrittlement plane, the block comprising the respective surface region; bonding the donor substrate to the receiver substrate via each block located at the bonding interface, after removing the mask; and detaching the donor substrate along the localized embrittlement planes to transfer blocks onto the receiver substrate.