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    Double-diffused MOS transistor and method of fabricating the same
    11.
    发明授权
    Double-diffused MOS transistor and method of fabricating the same 有权
    双扩散MOS晶体管及其制造方法

    公开(公告)号：US06194760B1

    公开(公告)日：2001-02-27

    申请号：US09215372

    申请日：1998-12-18

    Applicant: Sun-Hak Lee

    Inventor： Sun-Hak Lee

    IPC: H01L2972

    CPC classification number: H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/7809

    Abstract: There are provided a double-diffused MOS (Metal Oxide Semiconductor) transistor and a fabricating method thereof. In the double-diffused MOS transistor, a buried layer of a first conductive type and an epitaxial layer of the first conductive type are sequentially formed on a semiconductor substrate, and a gate electrode is formed on the epitaxial layer of the first conductive type with interposition of a gate insulating film. Source and drain regions of the first conductive type are formed in the surface of the epitaxial layer of the first conductive type in self-alignment and non-self-alignment with the gate electrode, respectively. A body region of a second conductive type is formed in the surface of the epitaxial layer of the first conductive type to be surrounded by the source region of the first conductive type, and a bulk bias region of the second conductive type is formed in the body region of the second conductive type under the source region of the first conductive type.

    Abstract translation: 提供双扩散MOS（金属氧化物半导体）晶体管及其制造方法。 在双扩散MOS晶体管中，在半导体衬底上依次形成第一导电类型和第一导电类型的外延层的掩埋层，并且在具有插入的第一导电类型的外延层上形成栅电极 的栅极绝缘膜。 第一导电类型的源极和漏极区分别以与栅电极自对准和非自对准的方式形成在第一导电类型的外延层的表面中。 第二导电类型的体区形成在第一导电类型的外延层的表面中，以被第一导电类型的源极区围绕，并且第二导电类型的体偏压区域形成在主体中 在第一导电类型的源极区域下的第二导电类型的区域。

    Semiconductor device and method of fabricating the same
    12.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08476700B2

    公开(公告)日：2013-07-02

    申请号：US12656671

    申请日：2010-02-12

    Applicant: Young-Mok Kim ,  Sun-Hak Lee ,  Tae-Cheol Lee ,  Yong-Sang Jeong

    Inventor： Young-Mok Kim ,  Sun-Hak Lee ,  Tae-Cheol Lee ,  Yong-Sang Jeong

    IPC: H01L29/66

    CPC classification number: H01L29/4236 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/1037 ,  H01L29/7834

    Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.

    Abstract translation: 半导体器件包括衬底中的凹槽，栅极绝缘层包括第一部分和第二部分，第一部分具有第一厚度并覆盖凹槽的侧壁的下部和凹槽的底表面， 并且所述第二部分具有第二厚度并且覆盖所述凹槽的侧壁的上部，所述第二厚度大于所述第一厚度，填充所述凹陷沟槽的栅电极，具有第一浓度的第一杂质区域并且设置在相对的位置 栅极电极的侧面，以及具有大于第一浓度的第二浓度的第二杂质区域，并且设置在第一杂质区域上以对应于栅极绝缘层的第二部分。

    High power address driver and display device employing the same
    15.
    发明申请
    High power address driver and display device employing the same 审中-公开
    大功率地址驱动器和使用该驱动器的显示设备

    公开(公告)号：US20090009434A1

    公开(公告)日：2009-01-08

    申请号：US12213936

    申请日：2008-06-26

    Applicant: Yong-Don Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Yong-Chan Kim ,  Sun-Hak Lee

    Inventor： Yong-Don Kim ,  Joung-Ho Kim ,  Mueng-Ryul Lee ,  Yong-Chan Kim ,  Sun-Hak Lee

    IPC: G09G3/28 ,  H03K19/094 ,  G09G5/00

    CPC classification number: G09G3/2965 ,  G09G3/293 ,  G09G3/296 ,  G09G2330/021 ,  G09G2330/028

    Abstract: An address driver includes an energy recovery circuit and an output stage connected to the energy recovery circuit. The output stage is connected to the energy recovery circuit and is formed of a pull-up MOS transistor and a pull-down MOS transistor in series. A source terminal of the pull-up MOS transistor is connected to the energy recovery circuit, and a bulk terminal of the pull-up MOS transistor is connected to a node providing a reverse bias between the source terminal and the bulk terminal of the pull-up MOS transistor. A display device employing the address driver is also provided.

    Abstract translation: 地址驱动器包括能量恢复电路和连接到能量恢复电路的输出级。 输出级与能量恢复电路相连，由串联的上拉MOS晶体管和下拉式MOS晶体管构成。 上拉MOS晶体管的源极端子连接到能量恢复电路，并且上拉MOS晶体管的体式端子连接到在源极端子和拉出型MOS晶体管的体式端子之间提供反向偏置的节点， up MOS晶体管。 还提供了采用地址驱动器的显示装置。

    Method of fabricating semiconductor device having gate dielectrics with different thicknesses
    16.
    发明授权
    Method of fabricating semiconductor device having gate dielectrics with different thicknesses 有权
    制造具有不同厚度的栅极电介质的半导体器件的方法

    公开(公告)号：US07446000B2

    公开(公告)日：2008-11-04

    申请号：US11826714

    申请日：2007-07-18

    Applicant: Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

    Inventor： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

    IPC: H01L21/8234

    CPC classification number: H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

    Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

    Abstract translation: 可以提供制造包括具有不同厚度的栅极电介质的半导体器件的方法。 制造半导体器件的方法可以包括提供具有较高电压器件区域和较低电压器件区域的衬底，在衬底上形成抗氧化层，并选择性地去除衬底上的抗氧化层的部分。 该方法还可以包括在衬底上进行第一热氧化以在抗氧化层的选择性去除的部分上形成场氧化物层，去除设置在较高电压器件区上的抗氧化层，进行第二热氧化 在所述衬底上形成在所述较高电压器件区域上的中央较高电压栅极氧化物层，去除设置在所述较低电压器件区域上的所述抗氧化层，并在所述衬底上进行第三热氧化以形成低电压栅极氧化物层 在较低电压器件区域。

    HIGH FREQUENCY MOS TRANSISTOR, METHOD OF FORMING THE SAME, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME
    17.
    发明申请
    HIGH FREQUENCY MOS TRANSISTOR, METHOD OF FORMING THE SAME, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
    高频MOS晶体管，其形成方法以及制造包括其的半导体器件的方法

    公开(公告)号：US20080138946A1

    公开(公告)日：2008-06-12

    申请号：US12032377

    申请日：2008-02-15

    Applicant: Sun-Hak Lee

    Inventor： Sun-Hak Lee

    IPC: H01L29/06

    CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/66659 ,  H01L29/7835

    Abstract: In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

    Abstract translation: 在高频LDMOS晶体管中，在衬底上形成栅极结构。 在与栅极结构间隔开的衬底上形成以第一浓度掺杂第一类型杂质的漏极。 掺杂有低于第一浓度的第二浓度的第一种杂质的缓冲阱包围漏极的侧部和下部。 在缓冲阱和栅极结构之间形成掺杂有低于第二浓度的第三浓度的第一种杂质的轻掺杂漏极。 掺杂有第一浓度的第一类型杂质的源极相对于栅极结构形成在与栅极结构相邻并且与漏极相对的衬底上。 因此，在不增加栅极结构和漏极之间的电容的情况下，导通电阻随着LDMOS晶体管中的击穿电压增加而减小。

    Methods of fabricating high voltage MOSFET having doped buried layer
    18.
    发明授权
    Methods of fabricating high voltage MOSFET having doped buried layer 失效
    制造具有掺杂掩埋层的高压MOSFET的方法

    公开(公告)号：US07381621B2

    公开(公告)日：2008-06-03

    申请号：US11620091

    申请日：2007-01-05

    Applicant: Sun-hak Lee ,  Kwang-dong Yoo

    Inventor： Sun-hak Lee ,  Kwang-dong Yoo

    IPC: H01L21/336

    CPC classification number: H01L29/66613 ,  H01L29/1083 ,  H01L29/7833

    Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.

    Abstract translation: MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。 第二导电类型的源区和漏区设置在杂质区中。 源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。 轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。 漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。 轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。 在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。 阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。 然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

    Method of fabricating semiconductor device having gate dielectrics with different thicknesses
    19.
    发明申请
    Method of fabricating semiconductor device having gate dielectrics with different thicknesses 有权

    公开(公告)号：US20080124873A1

    公开(公告)日：2008-05-29

    申请号：US11826714

    申请日：2007-07-18

    Applicant: Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

    Inventor： Sun-hak Lee ,  Kwang-dong Yoo ,  Sang-bae Yi ,  Soo-cheol Lee ,  Mueng-ryul Lee

    IPC: H01L21/8236

    CPC classification number: H01L21/823857 ,  H01L21/82385 ,  H01L21/823892

    Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

    Vertical double diffused MOSFET and method of fabricating the same
    20.
    发明授权
    Vertical double diffused MOSFET and method of fabricating the same 有权
    垂直双扩散MOSFET及其制造方法

    公开(公告)号：US06867476B2

    公开(公告)日：2005-03-15

    申请号：US10396348

    申请日：2003-03-26

    Applicant: Sun-Hak Lee

    Inventor： Sun-Hak Lee

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/00

    CPC classification number: H01L29/66712 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/7809

    Abstract: In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the first conductivity type. A plurality of source areas are respectively located in the body areas and heavily doped with impurities of the first conductivity type. A plurality of bulk areas are respectively located adjacent the source areas and in the body areas, and are heavily doped with impurities of the second conductivity type. A well region partially surrounds the body areas collectively and is doped with impurities of the first conductivity.

    Abstract translation: 在DMOS器件中，漂移区位于衬底上并且轻掺杂有第一导电类型的杂质。 多个体区位于漂移区中，并掺杂有与第一导电类型相反的第二导电类型的杂质。 多个源区分别位于体区，并且重掺杂有第一导电类型的杂质。 多个体积区域分别位于源区域和身体区域中，并且重掺杂有第二导电类型的杂质。 阱区部分地围绕身体区域并且掺杂有第一导电性的杂质。

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