公开(公告)号：US20110291229A1

公开(公告)日：2011-12-01

申请号：US12831341

申请日：2010-07-07

Applicant: Sang-Jin BYEON ,  Jun-Gi Choi

Inventor： Sang-Jin BYEON ,  Jun-Gi Choi

IPC: H01L23/538 ,  H01L23/525 ,  H01L21/66

CPC classification number: H01L21/76879 ,  H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract translation: 半导体集成电路包括：半导体芯片; 通过芯片穿过设置在半导体芯片中的导电图案并切割导电图案; 以及设置在贯通芯片通孔的外周面上的绝缘图案，以使导电图案与贯通芯片通孔绝缘。

公开(公告)号：US20110241763A1

公开(公告)日：2011-10-06

申请号：US12840212

申请日：2010-07-20

Applicant: Jae Bum Ko ,  Sang Jin Byeon

Inventor： Jae Bum Ko ,  Sang Jin Byeon

IPC: H03K19/003

CPC classification number: G11C8/12

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

Abstract translation: 半导体装置包括单独的芯片指定代码设置块，其被配置为响应于多个芯片熔丝信号而生成具有不同代码值的多个独立芯片指定代码或其中至少两个具有相同代码值的单独芯片指定代码; 以及单个芯片激活块，其被配置为响应于所述多个芯片熔丝信号来比较所述多个独立芯片指定代码与芯片选择地址，并且基于所述比较的结果来启用多个单独芯片激活信号中的一个。

公开(公告)号：US20110210780A1

公开(公告)日：2011-09-01

申请号：US12839333

申请日：2010-07-19

Applicant: Jae Bum Ko ,  Sang Jin Byeon

Inventor： Jae Bum Ko ,  Sang Jin Byeon

IPC: H03L5/00

CPC classification number: G06F1/10

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract translation: 半导体集成电路包括：被配置为接收外部电压的多个芯片。 每个芯片检测到芯片之一的信号延迟特性，以产生具有与信号延迟特性对应的电平的内部电压。

公开(公告)号：US07907462B2

公开(公告)日：2011-03-15

申请号：US12005506

申请日：2007-12-26

Applicant: Sang-Jin Byeon

Inventor： Sang-Jin Byeon

IPC: G11C7/04 ,  G11C5/14

CPC classification number: G11C7/04 ,  G11C5/147 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4091

Abstract: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.

公开(公告)号：US07889574B2

公开(公告)日：2011-02-15

申请号：US12219572

申请日：2008-07-24

Applicant: Sang-Jin Byeon ,  Kang-Seol Lee

Inventor： Sang-Jin Byeon ,  Kang-Seol Lee

IPC: G11C7/10

CPC classification number: G11C7/12 ,  G11C7/06

Abstract: A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Abstract translation: 半导体存储器件采用夹具来防止闩锁。 为此，半导体存储器件包括用于对一对位线进行预充电和均衡的预充电/均衡单元，以及用于产生控制预充电/均衡单元的使能和禁能的控制信号的控制信号产生单元，其中控制 信号发生单元包括钳位单元，用于将其源极电压钳位到低于其体积偏压的电压电平。

公开(公告)号：US07545203B2

公开(公告)日：2009-06-09

申请号：US11526818

申请日：2006-09-26

Applicant: Sang-Jin Byeon ,  Seok-Cheol Yoon

Inventor： Sang-Jin Byeon ,  Seok-Cheol Yoon

IPC: G05F1/46 ,  H02M3/07

CPC classification number: G11C5/145

Abstract: An inter voltage generation circuit includes a pumping voltage generator to generate a pumping voltage, a level comparator to compare the pumping voltage level with a peripheral voltage level and output an enable signal depending on the comparison result, and a peripheral voltage generator to output a pumping enable signal according to the enable signal and generate a peripheral voltage according to the enable signal.

Abstract translation: 电压产生电路包括产生泵浦电压的泵浦电压发生器，用于将泵浦电压电平与外围电压电平进行比较的电平比较器，并根据比较结果输出使能信号;以及外围电压发生器，输出泵浦 根据使能信号使能信号，并根据使能信号产生外设电压。

公开(公告)号：US07420358B2

公开(公告)日：2008-09-02

申请号：US11319299

申请日：2005-12-27

Applicant: Sang-Jin Byeon ,  Seok-Cheol Yoon

Inventor： Sang-Jin Byeon ,  Seok-Cheol Yoon

IPC: G05F3/16 ,  G05F1/10

CPC classification number: G05F3/30

Abstract: An internal voltage generating apparatus adaptive to a temperature change includes a reference voltage circuit including a complementary to absolute temperature (CTAT) type transistor and a proportional to absolute temperature (PTAT) type transistor for generating a first to a third initial reference voltage signals. A buffer circuit for buffering a first, a second and a third initial reference voltage signal is included to generate a first, a second, and a third reference voltage signal in response to enable signals. An internal voltage generating circuit is included to generate an internal voltage signal based on the first, the second and the third reference voltage signal by using an inputted power voltage.

Abstract translation: 适于温度变化的内部电压发生装置包括包括与绝对温度（CTAT）型晶体管互补的参考电压电路和用于产生第一至第三初始参考电压信号的绝对温度（PTAT）型晶体管的比例。 包括用于缓冲第一，第二和第三初始参考电压信号的缓冲电路，以响应于使能信号产生第一，第二和第三参考电压信号。 包括内部电压产生电路，以通过使用输入的电源电压来产生基于第一，第二和第三参考电压信号的内部电压信号。

公开(公告)号：US20080061856A1

公开(公告)日：2008-03-13

申请号：US11819424

申请日：2007-06-27

Applicant: Sang Jin Byeon

Inventor： Sang Jin Byeon

IPC: H03L5/00 ,  G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage generator of a semiconductor integrated circuit includes a first driver that outputs an internal voltage by using an internal reference voltage during an active operation in accordance with a detection signal generated by using an external voltage and an active enable signal activated during an activation mode, and a second driver that outputs an internal voltage by using the internal reference voltage during the active operation in accordance with the active enable signal.

Abstract translation: 半导体集成电路的内部电压发生器包括：第一驱动器，其根据通过使用外部电压产生的检测信号和在激活模式下激活的有效使能信号，在有效操作期间使用内部参考电压来输出内部电压 以及第二驱动器，其根据有效使能信号在有效操作期间通过使用内部基准电压输出内部电压。

公开(公告)号：US20070080725A1

公开(公告)日：2007-04-12

申请号：US11528528

申请日：2006-09-28

Applicant: Sang-Jin Byeon ,  Seok-Cheol Yoon

Inventor： Sang-Jin Byeon ,  Seok-Cheol Yoon

IPC: H03L7/00

CPC classification number: G11C7/20 ,  G11C5/14 ,  G11C7/04 ,  H03K17/223

Abstract: A power-up signal generator of a semiconductor device includes a voltage dividing block, a level detection block, and an output block. The voltage dividing block outputs a divided voltage corresponding to a voltage level of an external power supply voltage. The level detection block is controlled according to the divided voltage, and comprises a pull-up unit and a pull-down unit. The output block outputs a power-up signal having a logic level corresponding to a voltage level of an output node of the level detection block. The pull-up unit and the pull-down unit have different threshold voltage levels with respect to a temperature change.

Abstract translation: 半导体器件的上电信号发生器包括分压块，电平检测块和输出块。 分压块输出对应于外部电源电压的电压电平的分压。 电平检测块根据分压控制，包括一个上拉单元和一个下拉单元。 输出块输出具有与电平检测块的输出节点的电压电平对应的逻辑电平的上电信号。 上拉单元和下拉单元相对于温度变化具有不同的阈值电压电平。

公开(公告)号：US20070001753A1

公开(公告)日：2007-01-04

申请号：US11321420

申请日：2005-12-29

Applicant: Sang-Jin Byeon

Inventor： Sang-Jin Byeon

IPC: G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage generation circuit of a semiconductor device includes: a comparator for comparing a reference voltage level with a detection voltage level to provide a comparison signal; an internal voltage output device for raising a voltage of an internal voltage output terminal to a predetermined level in response to the comparison signal; and an internal voltage output controller for controlling the internal voltage output terminal to be raised to a selected level. A voltage applied to the internal voltage output terminal is outputted as an internal voltage.