公开(公告)号：US20060003533A1

公开(公告)日：2006-01-05

申请号：US11082122

申请日：2005-03-16

Applicant: Thorsten Kammler ,  Scott Luning ,  Linda Black

Inventor： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract translation: 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。

公开(公告)号：US06821853B1

公开(公告)日：2004-11-23

申请号：US10159413

申请日：2002-05-31

Applicant: James F. Buller ,  Scott Luning

Inventor： James F. Buller ,  Scott Luning

IPC: H01L218234

CPC classification number: H01L21/823468 ,  H01L21/823462

Abstract: Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

Abstract translation: 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。

公开(公告)号：US06319804B1

公开(公告)日：2001-11-20

申请号：US08624910

申请日：1996-03-27

Applicant: David Greenlaw ,  Scott Luning

Inventor： David Greenlaw ,  Scott Luning

IPC: H01L2102

CPC classification number: H01L29/66575 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed. The blocking layer on the gate stack need not be removed, which aids in minimizing substrate damage and in prevention of shorting a source-drain contact region to the substrate.

Abstract translation: 本发明涉及用于独立地掺杂半导体器件的栅极和源极 - 漏极区域的方法。 该方法由该条款开始。 具有隔离区域和薄绝缘层的衬底。 在衬底上形成多晶硅层，其以第一掺杂级别掺杂有第一类型的掺杂剂。 在多晶硅层上形成能够承受1000℃的温度的导电层，并且在导电层上形成阻挡层。 蚀刻多晶硅层，导电层和阻挡层以形成栅叠层。 源极 - 漏极区域随后以第二掺杂水平掺杂第二类型的掺杂剂。 源极 - 漏极区域在1000℃的热循环中被激活，随后在源极 - 漏极区域上形成TiSi 2。 然后形成接触。 栅堆叠上的阻挡层不需要去除，这有助于最小化衬底损伤并防止将源 - 漏接触区域短路到衬底。

公开(公告)号：US6107149A

公开(公告)日：2000-08-22

申请号：US325628

申请日：1999-06-04

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，其包括具有减小的结电容的梯度结。 通过在源极/漏极注入之后在栅电极上形成第二侧壁间隔物并且将具有高扩散率的N型杂质（例如P）离子注入到A5植入物中，然后进行活化退火来实现渐变结。

公开(公告)号：US5935867A

公开(公告)日：1999-08-10

申请号：US481895

申请日：1995-06-07

Applicant: Roger Alvis ,  Scott Luning ,  Peter Griffin

Inventor： Roger Alvis ,  Scott Luning ,  Peter Griffin

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

Abstract: A process for forming a shallow, lightly doped region in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a surface; growing an oxide layer on the substrate, the oxide having a thickness; depositing a layer of polysilicon on the oxide; patterning the polysilicon layer and the oxide layer to provide a gate structure; and implanting into the substrate a source and a drain region about the gate structure at an angle less than 90 degrees with respect to the surface of the substrate.

Abstract translation: 一种用于在半导体器件中形成浅的，轻掺杂区域的工艺。 该方法包括提供具有表面的半导体衬底的步骤; 在衬底上生长氧化物层，氧化物具有厚度; 在氧化物上沉积多晶硅层; 图案化多晶硅层和氧化物层以提供栅极结构; 以及相对于所述衬底的表面以小于90度的角度将围绕所述栅极结构的源极和漏极区域注入到所述衬底中。

公开(公告)号：US08120120B2

公开(公告)日：2012-02-21

申请号：US12561685

申请日：2009-09-17

Applicant: Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

Inventor： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

Abstract translation: 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US20110204446A1

公开(公告)日：2011-08-25

申请号：US13098065

申请日：2011-04-29

Applicant: Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

Inventor： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC: H01L29/78

CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US20090283806A1

公开(公告)日：2009-11-19

申请号：US12121387

申请日：2008-05-15

Applicant: Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

Inventor： Frank Bin YANG ,  Andrew M. WAITE ,  Scott Luning

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US07521380B2

公开(公告)日：2009-04-21

申请号：US11738828

申请日：2007-04-23

Applicant: Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

Inventor： Andrew M. Waite ,  Scott Luning ,  Frank (Bin) Yang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

Abstract translation: 提供了一种在半导体衬底上制造半导体器件的方法。 在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。 沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。 覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。 去除覆盖在NPT上的蚀刻停止层的暴露部分。

公开(公告)号：US20080220579A1

公开(公告)日：2008-09-11

申请号：US11683174

申请日：2007-03-07

Applicant: Rohit PAL ,  David BROWN ,  Scott LUNING

Inventor： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC: H01L21/336 ,  H01L29/94

CPC classification number: H01L29/0847 ,  H01L21/31662 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

Abstract: According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.

Abstract translation: 根据用于制造在半导体衬底的表面具有沟道区的应力增强型MOS器件的方法，第一和第二沟槽被蚀刻到半导体衬底中，第一沟槽具有第一侧表面，并且第二沟槽具有第二沟槽 侧面。 第一和第二侧表面跨越通道区域形成。 然后将第一和第二侧表面在受控的氧化环境中氧化，从而生长氧化物区域。 然后去除氧化物区域，从而将第一和第二侧表面重新定位成更靠近沟道区域。 在第一和第二侧表面重新定位时，第一和第二沟槽被填充有SiGe。