公开(公告)号：US06319804B1

公开(公告)日：2001-11-20

申请号：US08624910

申请日：1996-03-27

申请人： David Greenlaw ,  Scott Luning

发明人： David Greenlaw ,  Scott Luning

IPC分类号： H01L2102

CPC分类号： H01L29/66575 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed. The blocking layer on the gate stack need not be removed, which aids in minimizing substrate damage and in prevention of shorting a source-drain contact region to the substrate.

摘要翻译： 本发明涉及用于独立地掺杂半导体器件的栅极和源极 - 漏极区域的方法。 该方法由该条款开始。 具有隔离区域和薄绝缘层的衬底。 在衬底上形成多晶硅层，其以第一掺杂级别掺杂有第一类型的掺杂剂。 在多晶硅层上形成能够承受1000℃的温度的导电层，并且在导电层上形成阻挡层。 蚀刻多晶硅层，导电层和阻挡层以形成栅叠层。 源极 - 漏极区域随后以第二掺杂水平掺杂第二类型的掺杂剂。 源极 - 漏极区域在1000℃的热循环中被激活，随后在源极 - 漏极区域上形成TiSi 2。 然后形成接触。 栅堆叠上的阻挡层不需要去除，这有助于最小化衬底损伤并防止将源 - 漏接触区域短路到衬底。

公开(公告)号：US08193592B2

公开(公告)日：2012-06-05

申请号：US12904662

申请日：2010-10-14

申请人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

发明人： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US08148214B2

公开(公告)日：2012-04-03

申请号：US12360961

申请日：2009-01-28

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/00

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20110062498A1

公开(公告)日：2011-03-17

申请号：US12561685

申请日：2009-09-17

申请人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

发明人： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

摘要翻译： 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US07893493B2

公开(公告)日：2011-02-22

申请号：US11456326

申请日：2006-07-10

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L27/12 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

摘要翻译： 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。

公开(公告)号：US07674720B2

公开(公告)日：2010-03-09

申请号：US12131214

申请日：2008-06-02

申请人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

发明人： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

摘要翻译： 公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US07223662B2

公开(公告)日：2007-05-29

申请号：US11082122

申请日：2005-03-16

申请人： Thorsten Kammler ,  Scott Luning ,  Linda Black

发明人： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

摘要： By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

摘要翻译： 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。

公开(公告)号：US20060252191A1

公开(公告)日：2006-11-09

申请号：US11120857

申请日：2005-05-03

申请人： Thorsten Kammler ,  Helmut Bierstedt ,  Scott Luning

发明人： Thorsten Kammler ,  Helmut Bierstedt ,  Scott Luning

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/0206 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78621

摘要： A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

摘要翻译： 第一栅极结构和第二栅极结构形成在半导体衬底上。 第一保护层形成在第一栅极结构和相关源极漏极区之上。 在去除第一保护层之前，在第二源极漏极上形成第一外延层。

公开(公告)号：US20060003533A1

公开(公告)日：2006-01-05

申请号：US11082122

申请日：2005-03-16

申请人： Thorsten Kammler ,  Scott Luning ,  Linda Black

发明人： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

摘要： By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

摘要翻译： 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。

公开(公告)号：US06821853B1

公开(公告)日：2004-11-23

申请号：US10159413

申请日：2002-05-31

申请人： James F. Buller ,  Scott Luning

发明人： James F. Buller ,  Scott Luning

IPC分类号： H01L218234

CPC分类号： H01L21/823468 ,  H01L21/823462

摘要： Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

摘要翻译： 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。