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    Method and vector organism for controlled accumulation of cloned heterologous gene products in Bacillus subtilis
    12.
    发明授权
    Method and vector organism for controlled accumulation of cloned heterologous gene products in Bacillus subtilis 失效
    用于在枯草芽孢杆菌中克隆的异源基因产物的控制积累的方法和载体生物体

    公开(公告)号：US4711843A

    公开(公告)日：1987-12-08

    申请号：US461248

    申请日：1983-01-26

    申请人： Shing Chang

    发明人： Shing Chang

    IPC分类号： C12N9/86 ,  C12N15/67 ,  C12P21/00 ,  C07H21/04 ,  C12N1/00 ,  C12N1/20 ,  C12N15/00 ,  C12P19/34 ,  C12P21/02 ,  C12P21/04 ,  C12R1/125 ,  C12R1/19

    CPC分类号： C12N9/86 ,  C12N15/67 ,  C07K2319/02 ,  C07K2319/036 ,  C07K2319/61 ,  Y10S435/839 ,  Y10S435/849 ,  Y10S930/30

    摘要： A method and a cloning vector are described for the controlled accumulation of cloned heterologous gene products in Bacillus subtilis. The cloning vector is capable of being replicated in B. subtilis and includes the heterologous gene located and oriented such as to be under the control of an operator, promoter, and ribosomal binding site sequence. The gene codes for a protein which is under the control of a transport mechanism by which the protein is secreted by the B. subtilis. The gene product is recovered from the growth medium for the B. subtilis. The cloning vector is also capable of similar use in other bacteria such as E. coli.

    摘要翻译： 描述了克隆的异源基因产物在枯草芽孢杆菌中的受控积累的方法和克隆载体。 克隆载体能够在枯草芽孢杆菌中复制，并且包括位于和定向的异源基因，以便在操纵子，启动子和核糖体结合位点序列的控制下。 该基因编码一种蛋白质，其由蛋白质被枯草芽孢杆菌分泌的转运机制控制。 从枯草芽孢杆菌的生长培养基中回收基因产物。 克隆载体也能够在其他细菌如大肠杆菌中类似地使用。

    Chimeric plasmids that replicate in bacteria and yeast and microorganisms transformed therewith
    13.
    发明授权
    Chimeric plasmids that replicate in bacteria and yeast and microorganisms transformed therewith 失效
    在细菌和酵母中复制的嵌合质粒和用其转化的微生物

    公开(公告)号：US4477571A

    公开(公告)日：1984-10-16

    申请号：US346258

    申请日：1982-02-05

    申请人： Shing Chang ,  James H. Meade

    发明人： Shing Chang ,  James H. Meade

    IPC分类号： C12N1/18 ,  C12N1/20 ,  C12N15/00 ,  C12N15/68 ,  C12N15/81 ,  C12N1/00

    CPC分类号： C12N15/81 ,  C12N15/68

    摘要： Chimeric plasmids capable of transforming bacteria and yeast are described. The plasmids carry the Cm (chloramphenicol resistance) gene and the Tc (tetracycline resistance) gene as selectable markers. The Cm gene allows the plasmids to be selected for in wild-type strains of the yeast Saccharomyces cerevisiae. The Tc gene allows heterologous genes cloned into the plasmids to be selected for in Escherichia coli bacteria.

    摘要翻译： 描述了能够转化细菌和酵母的嵌合质粒。 质粒携带Cm（氯霉素抗性）基因和Tc（四环素抗性）基因作为选择标记。 Cm基因允许在酵母酿酒酵母的野生型菌株中选择质粒。 Tc基因允许在大肠杆菌细菌中选择克隆到质粒中的异源基因。

    White line skipping
    14.
    发明授权
    White line skipping 失效
    白线跳过

    公开(公告)号：US4413287A

    公开(公告)日：1983-11-01

    申请号：US368258

    申请日：1982-04-14

    申请人： John D. Torpie ,  Robert F. Lozen ,  Shing-Chang R. Hsieh

    发明人： John D. Torpie ,  Robert F. Lozen ,  Shing-Chang R. Hsieh

    IPC分类号： H04N1/17 ,  H04N1/403 ,  H04N1/40

    CPC分类号： H04N1/403 ,  H04N1/17

    摘要： A white line skipping technique for data reduction is disclosed for reducing facsimile transmission time. Video processing for white line skipping centers around the use of a five element solid state linear array. The photosensitive area for each of the five elements corresponds to a single picture element for the defined resolution parameters. VID 0 is the active video signal and is processed in the normal manner for transmission. VID 1 through VID 4 comprise the look ahead scan elements. The slicing level is derived from the VID 0 peak detector which controls the video automatic gain control. Any black video elements encountered during a scan line causes a flip-flop to be set. At the end of each scan line, corresponding to one complete drum revolution, and during the lost time interval, the status of each flip-flop is sampled by the microprocessor to determine whether the scan line is entire white. The flip-flops are then reset for the next scan or drum revolution.

    摘要翻译： 公开了用于减少传真传输时间的白线跳过技术。 用于白线跳过的视频处理围绕使用五元素固态线性阵列。 五个元件中的每一个的光敏区域对应于用于定义的分辨率参数的单个图像元素。 VID 0是有效的视频信号，并以正常方式进行处理以进行传输。 VID 1至VID 4包括前瞻扫描元件。 切片电平从控制视频自动增益控制的VID 0峰值检测器导出。 在扫描线期间遇到的任何黑色视​​频元件都会触发一个触发器。 在每个扫描线的末端，对应于一个完整的转鼓旋转，并且在丢失的时间间隔期间，每个触发器的状态由微处理器采样，以确定扫描线是否是整个白色。 然后复位触发器进行下一次扫描或转鼓旋转。

    LED reflector molding process, construction, and loader thereof
    16.
    发明申请
    LED reflector molding process, construction, and loader thereof 失效
    LED反射器成型工艺，结构及装载机

    公开(公告)号：US20070263389A1

    公开(公告)日：2007-11-15

    申请号：US11707241

    申请日：2007-02-16

    申请人： Chen-Shing Chang ,  Jung-Hsiu Hsieh ,  Kuo Chen ,  Min-Li Lee

    发明人： Chen-Shing Chang ,  Jung-Hsiu Hsieh ,  Kuo Chen ,  Min-Li Lee

    IPC分类号： F21V7/22

    CPC分类号： F21V7/22 ,  F21S41/37 ,  H01L33/46 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A light emitting diode reflector molding process, and a construction thereof includes preparation of a first and a second green sheet structures respectively provided with a first and a second open patterns with the porosity of the second open pattern smaller than that of the first open pattern; the second green sheet structure being placed on top of the first green sheet structure to such that both opening patterns being overlapped to each; a metallic layer being coated on the second green sheet structure, the second green sheet structure being molded along the opening pattern of and covering upon the first green sheet for the metallic layer to become the wall of the reflector opening.

    摘要翻译： 发光二极管反射器成型工艺及其结构包括制备分别设置有第一开放图案的孔隙率小于第一开放图案的第一和第二开放图案的第一和第二生片结构; 所述第二生片结构被放置在所述第一生片结构的顶部上，使得两个开口图案都重叠; 金属层被涂覆在第二生片结构上，第二生片结构沿着开口图案模制并覆盖在第一生金属层上以成为反射器开口的壁。

    Method and system for forming source regions in memory devices
    17.
    发明授权
    Method and system for forming source regions in memory devices 有权
    用于在存储器件中形成源区的方法和系统

    公开(公告)号：US07227218B2

    公开(公告)日：2007-06-05

    申请号：US11094035

    申请日：2005-03-30

    申请人： Yi-Shing Chang ,  Wen-Ting Chu

    发明人： Yi-Shing Chang ,  Wen-Ting Chu

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

    摘要翻译： 公开了一种存储器件及其制造方法。 该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和 第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。 源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。 此外，控制门材料填充在第三开口中。

    Self-aligned non-volatile memory and method of forming the same
    18.
    发明申请
    Self-aligned non-volatile memory and method of forming the same 审中-公开
    自对准非易失性存储器及其形成方法

    公开(公告)号：US20060068546A1

    公开(公告)日：2006-03-30

    申请号：US10951688

    申请日：2004-09-29

    申请人： Yi-Shing Chang

    发明人： Yi-Shing Chang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

    摘要： A non-volatile memory is described. A substrate comprising a stacked layer is provided. A sacrificial layer is deposited and patterned to form a first opening. A first spacer is formed on sidewalls of the first opening, and the stacked layer is etched using the first spacer as a first mask to form a second opening. An isolation layer is formed in a portion of the first and the second openings, and a conductive filling layer is formed thereon. The stacked layer is etched using a portion of the conductive filling layer as a second mask.

    摘要翻译： 描述非易失性存储器。 提供了包括层叠层的基板。 牺牲层被沉积并图案化以形成第一开口。 第一间隔件形成在第一开口的侧壁上，并且使用第一间隔件作为第一掩模蚀刻叠层，以形成第二开口。 在第一和第二开口的一部分中形成隔离层，并且在其上形成导电填充层。 使用导电填充层的一部分作为第二掩模蚀刻堆叠层。

    Method and system for forming source regions in memory devices
    19.
    发明授权
    Method and system for forming source regions in memory devices 失效

    公开(公告)号：US06890821B2

    公开(公告)日：2005-05-10

    申请号：US10617470

    申请日：2003-07-11

    申请人： Yi-Shing Chang ,  Wen-Ting Chu

    发明人： Yi-Shing Chang ,  Wen-Ting Chu

    IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.