公开(公告)号：US20080132022A1

公开(公告)日：2008-06-05

申请号：US11938064

申请日：2007-11-09

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and′ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和“大的注入量”的阱区域。 在进行掺杂剂的活化热处理后，将源极/漏极区域的表面制成硅化硅12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US20080080225A1

公开(公告)日：2008-04-03

申请号：US11865095

申请日：2007-10-01

申请人： Shinichi FUKADA

发明人： Shinichi FUKADA

IPC分类号： G11C11/22 ,  G11C7/00

CPC分类号： G11C11/22 ,  G11C7/24

摘要： A semiconductor memory device includes: a memory section; and a control section that controls writing and reading of data with respect to the memory section, wherein the memory section includes a first memory region formed from nonvolatile memory cells, each of the memory cells storing binary data corresponding to a first polarization state and a second polarization state; and the control section controls, for all of the memory cells included in the first memory region, such that, before writing data to each of the memory cells based on new data externally inputted, the memory cell is polarized in the first polarization state, and then the memory cell is further polarized in the second polarization state.

摘要翻译： 半导体存储器件包括：存储器部分; 以及控制部分，其控制相对于存储器部分的数据的写入和读取，其中存储器部分包括由非易失性存储器单元形成的第一存储器区域，每个存储器单元存储对应于第一偏振态的二进制数据和第二存储器单元 极化状态; 并且所述控制部对于包含在所述第一存储区域中的所有存储单元进行控制，使得在基于从外部输入的新数据向所述存储单元写入数据之前，所述存储单元在所述第一偏振状态下极化， 那么存储单元在第二偏振状态下被进一步极化。

公开(公告)号：US20070284637A1

公开(公告)日：2007-12-13

申请号：US11806618

申请日：2007-06-01

申请人： Shinichi Fukada

发明人： Shinichi Fukada

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

公开(公告)号：US20070184603A1

公开(公告)日：2007-08-09

申请号：US11783187

申请日：2007-04-06

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US20070133031A1

公开(公告)日：2007-06-14

申请号：US11567049

申请日：2006-12-05

申请人： Yoichi Takaragi ,  Shinichi Fukada ,  Tsutomu Murayama ,  Kunio Yoshihara

发明人： Yoichi Takaragi ,  Shinichi Fukada ,  Tsutomu Murayama ,  Kunio Yoshihara

IPC分类号： G06F3/12

CPC分类号： G06K15/02

摘要： An image processing apparatus includes a receiving unit configured to externally receive print data including information on an attribute of an image to print, a rasterizing unit configured to generate raster image data based on the print data received by the receiving unit, an attribute data generating unit configured to generate attribute data representing an attribute of an image included in the raster image data generated by the rasterizing unit based on the information on an attribute of an image to print included in the print data, and a vectorizing unit configured to vectorize at least a part of the raster image data. The vectorizing unit identifies the attribute of the image included in the raster image data based on the attribute data generated by the attribute data generating unit, and performs vectorization based on the identified attribute of the image.

摘要翻译： 一种图像处理装置，包括：接收单元，被配置为从外部接收包括关于要打印的图像的属性的信息的打印数据;光栅化单元，被配置为基于由所述接收单元接收的打印数据生成光栅图像数据;属性数据生成单元 被配置为基于关于打印数据中包含的要打印的图像的属性的信息，生成表示由光栅化单元生成的光栅图像数据中包含的图像的属性的属性数据，以及矢量化单元， 部分光栅图像数据。 矢量化单元基于由属性数据生成单元生成的属性数据来识别包含在光栅图像数据中的图像的属性，并且基于所识别的图像的属性来执行矢量化。

公开(公告)号：US20070004163A1

公开(公告)日：2007-01-04

申请号：US11519907

申请日：2006-09-13

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/331

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US07094642B2

公开(公告)日：2006-08-22

申请号：US11110693

申请日：2005-04-21

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US20060099722A1

公开(公告)日：2006-05-11

申请号：US11226728

申请日：2005-09-14

申请人： Hiroyuki Mitsui ,  Katsuo Takano ,  Shinichi Fukada ,  Hiroshi Matsuki

发明人： Hiroyuki Mitsui ,  Katsuo Takano ,  Shinichi Fukada ,  Hiroshi Matsuki

IPC分类号： H01L21/00

CPC分类号： H01L28/57 ,  H01L27/11507 ,  H01L28/65

摘要： A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.

摘要翻译： 制造铁电存储器的方法包括：（a）在形成在基底基板上的第一电介质层上形成第一和第二接触部分; （b）依次层叠具有下电极，铁电层和上电极的叠层体; （c）在层叠体上形成导电硬掩模，并蚀刻通过硬掩模暴露的层叠体的区域，从而在第一接触部分上形成铁电电容器; （d）在所述第一电介质层的上方形成覆盖所述硬掩模，所述强电介质电容器和所述第二接触部的第二电介质层; （e）在所述第二电介质层中形成暴露所述第二接触部分的接触孔; （f）在包括用于形成第三接触部分的接触孔的区域中提供导电层; 和（g）研磨导电层和第二介电层，直到暴露铁电电容器上方的硬掩模。

公开(公告)号：US07018854B2

公开(公告)日：2006-03-28

申请号：US10849016

申请日：2004-05-20

申请人： Shinichi Fukada

发明人： Shinichi Fukada

IPC分类号： H01L21/00 ,  H01L21/8242 ,  H01L21/20 ,  H01L31/119 ,  H01L29/76 ,  H01L29/94

CPC分类号： G11C11/22 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/60 ,  Y10S438/942

摘要： The invention provides a semiconductor device and a method for manufacturing the same that are capable of improving the product performance and operational efficiency of a cross-point FeRAM, as well as increasing the area of capacitors included in the cross-point FeRAM. An upper electrode supporting layer forming mask for forming an upper electrode supporting layer can be made of a hard mask material. By making use of the upper electrode supporting layer forming mask remaining unremoved in forming and processing a lower electrode layer, prior to forming an upper electrode layer, a region where a ferroelectric capacitor is formed can be made larger than an area occupied by an intersection of the upper electrode layer and the lower electrode layer.

摘要翻译： 本发明提供了能够提高交叉点FeRAM的产品性能和操作效率以及增加交叉点FeRAM中包括的电容器面积的半导体器件及其制造方法。 用于形成上电极支撑层的上电极支撑层形成掩模可以由硬掩模材料制成。 通过在形成和处理下电极层的同时利用保持不被去除的上电极支撑层形成掩模，在形成上电极层之前，可以使形成铁电电容器的区域大于由交叉 上电极层和下电极层。

公开(公告)号：US20060046318A1

公开(公告)日：2006-03-02

申请号：US11210010

申请日：2005-08-23

申请人： Mamoru Ueda ,  Kazuhiro Masuda ,  Shinichi Fukada

发明人： Mamoru Ueda ,  Kazuhiro Masuda ,  Shinichi Fukada

IPC分类号： H01L21/00

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

摘要翻译： 铁电存储器包括基底构件，形成在基底构件上的第一电介质层，形成在第一电介质层上方的第二电介质层，穿透第一和第二电介质层的接触孔，形成在接触孔中的插塞，以及 形成在插塞上方的阻挡层，以及由下电极，强电介质层和上电极形成的强电介质电容器，其连续地层压在包括在插塞上方的区域中。 第二电介质层具有比插塞和第一电介质层更难以抛光的性质。