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    Architecture for routing resources in a field programmable gate array
    14.
    发明授权
    Architecture for routing resources in a field programmable gate array 失效
    用于在现场可编程门阵列中路由资源的架构

    公开(公告)号：US07579868B2

    公开(公告)日：2009-08-25

    申请号：US11843575

    申请日：2007-08-22

    Applicant: Sinan Kaptanoglu

    Inventor： Sinan Kaptanoglu

    IPC: H01L25/00

    CPC classification number: H03K19/17736 ,  H03K19/17796

    Abstract: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a plurality of matrices of intersecting interconnect conductors in the routing channels. A first number of reprogrammable elements is disposed at intersections in at least one of the plurality of matrices, a second number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The second number of reprogrammable elements is greater than the first number of reprogrammable elements, and a third number of reprogrammable elements disposed at intersections in at least one of the plurality of matrices. The third number of reprogrammable elements is greater than the second number of reprogrammable elements.

    Abstract translation: 一种用于在现场可编程门阵列中路由信道的转动结构，包括具有第一方向的第一多个路由信道和具有第二方向的第二多个路由信道。 第一多个路由信道与第二多个路由信道相交，以在路由信道中形成多个交叉互连导体矩阵。 第一数量的可编程元件设置在多个矩阵中的至少一个矩阵中的交点处，第二数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第二数量的可再编程元件大于第一数量的可再编程元件，并且第三数量的可重新编程元件设置在多个矩阵中的至少一个矩阵中的相交处。 第三数量的可编程元件大于第二数量的可编程元件。

    Block level routing architecture in a field programmable gate array
    15.
    发明授权
    Block level routing architecture in a field programmable gate array 失效
    块级路由架构在现场可编程门阵列中

    公开(公告)号：US07557611B2

    公开(公告)日：2009-07-07

    申请号：US12034555

    申请日：2008-02-20

    Applicant: Sinan Kaptanoglu

    Inventor： Sinan Kaptanoglu

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H01L27/11803

    Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy is are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Board (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.

    Abstract translation: FPGA架构具有顶级，中级和低级。 该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。 在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。 中层层次的B16x16瓦片是16块16块阵列。 中层层次的路由资源是包括互连导体组的高速公路路由信道M1，M2和M3。 在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。 每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M1，M2和M3提供每个B1块的接入。 每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。 每组三个互连导体连接到扩展板（EB）3x3开关矩阵的第一侧。 每个EB 3x3开关矩阵的第二面耦合到E-tab。 在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

    Dedicated crossbar and barrel shifter block on programmable logic resources
    17.
    发明授权
    Dedicated crossbar and barrel shifter block on programmable logic resources 有权
    专用的横杆和桶形移位器块可编程逻辑资源

    公开(公告)号：US07355442B1

    公开(公告)日：2008-04-08

    申请号：US11371451

    申请日：2006-03-08

    Applicant: Michael Hutton ,  Sinan Kaptanoglu

    Inventor： Michael Hutton ,  Sinan Kaptanoglu

    IPC: G06F7/38 ,  H03K19/177

    CPC classification number: H03K19/17736 ,  G06F5/01 ,  G06F7/766 ,  H03K19/17732

    Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

    Abstract translation: 提供专用硬件块用于在可编程逻辑资源中实现十字路口和/或桶形移位器。 横杆和/或桶形移位器电路可以替代可编程逻辑资源上的可编程逻辑区域的一行或多行，一列或多列，一个或多个矩形或其任意组合。 可以通过实施时间复用来进一步改进交叉开关和/或桶形移位器电路的功能。

    Block symmetrization in a field programmable gate array
    18.
    发明授权
    Block symmetrization in a field programmable gate array 失效
    在现场可编程门阵列中的块对称

    公开(公告)号：US07233167B1

    公开(公告)日：2007-06-19

    申请号：US11056984

    申请日：2005-02-11

    Applicant: Sinan Kaptanoglu

    Inventor： Sinan Kaptanoglu

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17796

    Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

    Abstract translation: FPGA架构具有顶级，中级和低级。 顶级是由I / O块包围的B16x16瓦数组。 中间路由资源是高速公路路由信道，包括互连导体。 在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。 每个B1块包括四组设备。 每个簇包括第一和第二LUT3，LUT2和DFF。 每个LUT3有三个输入和一个输出。 每个LUT2有两个输入和一个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

    Area efficient fractureable logic elements
    19.
    发明申请
    Area efficient fractureable logic elements 有权
    区域有效的可断裂逻辑元件

    公开(公告)号：US20070063732A1

    公开(公告)日：2007-03-22

    申请号：US11234538

    申请日：2005-09-22

    Applicant: Sinan Kaptanoglu ,  Bruce Pedersen ,  James Schleicher ,  Jinyong Yuan ,  Michael Hutton ,  David Lewis

    Inventor： Sinan Kaptanoglu ,  Bruce Pedersen ,  James Schleicher ,  Jinyong Yuan ,  Michael Hutton ,  David Lewis

    IPC: H03K19/177

    CPC classification number: H03K19/1737

    Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

    Abstract translation: 可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。 每个2-LUT包括四个存储元件。 每个存储器元件被配置为保持一个数据位。 可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。 当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。 当控制电路在第二模式下操作时，使用该组六个输入和第一和第二2-LUTS中的三个的第一子集来生成第二组合输出。 另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集 一组六个输入。

    Arithmetic structures for programmable logic devices
    20.
    发明授权
    Arithmetic structures for programmable logic devices 有权
    可编程逻辑器件的算术结构

    公开(公告)号：US07185035B1

    公开(公告)日：2007-02-27

    申请号：US10693576

    申请日：2003-10-23

    Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu

    Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu

    IPC: G06F7/38

    CPC classification number: G06F7/501 ,  G06F2207/4816

    Abstract: According to some embodiments, arithmetic structures in logic elements result from combining inverters and pass gates (or other multiplexing hardware) with LUT hardware. According to other embodiments, arithmetic structures in logic elements result from combining dedicated adder hardware (e.g., including XOR units) and fracturable LUT hardware. According to other embodiments, arithmetic structures in logic elements result from providing complementary input connections between multiplexers and LUT hardware. In this way, the present invention enables the incorporation of arithmetic structures with LUT structures in a number of ways.

    Abstract translation: 根据一些实施例，逻辑元件中的算术结构源于将反相器和传递门（或其他多路复用硬件）与LUT硬件组合。 根据其他实施例，逻辑元件中的算术结构源于组合专用加法器硬件（例如，包括XOR单元）和可分解LUT硬件。 根据其他实施例，逻辑元件中的算术结构源于在多路复用器和LUT硬件之间提供互补的输入连接。 以这种方式，本发明能够以多种方式结合具有LUT结构的算术结构。

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