公开(公告)号：US06869874B2

公开(公告)日：2005-03-22

申请号：US10330303

申请日：2002-12-30

Applicant: Hai-Won Kim ,  Su-Jin Chae

Inventor： Hai-Won Kim ,  Su-Jin Chae

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/44

CPC classification number: H01L27/10888 ,  H01L21/76897

Abstract: The present invention provides a method for forming a contact plug of a semiconductor device with a low contact resistance. The inventive method includes the steps of: forming a contact hole in an inter-layer insulating layer formed on a silicon substrate; removing a native oxide layer formed in the contact hole; forming a single crystal silicon layer on a surface of the silicon substrate in the contact hole, wherein the single crystal silicon layer is formed by an epitaxial growth performed at a first reaction chamber of which pressure is maintained less than approximately 10−6 Torr; and filling the contact hole with polysilicon, wherein the polysilicon layer is formed at a second reaction chamber.

Abstract translation: 本发明提供一种形成具有低接触电阻的半导体器件的接触插塞的方法。 本发明的方法包括以下步骤：在形成在硅衬底上的层间绝缘层中形成接触孔; 去除形成在接触孔中的自然氧化物层; 在所述接触孔中的所述硅衬底的表面上形成单晶硅层，其中所述单晶硅层通过外延生长形成，所述外延生长在第一反应室中进行，其中所述第一反应室的压力保持在小于约10 -6 Torr ; 以及用多晶硅填充所述接触孔，其中所述多晶硅层在第二反应室处形成。

公开(公告)号：US20130099188A1

公开(公告)日：2013-04-25

申请号：US13331254

申请日：2011-12-20

Applicant: Jin Hyock Kim ,  Su Jin Chae ,  Young Seok Kwon

Inventor： Jin Hyock Kim ,  Su Jin Chae ,  Young Seok Kwon

IPC: H01L47/00

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

Abstract: A phase change memory device including a multi-level cell and a method of manufacturing the same are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from a heating electrode.

Abstract translation: 提供一种包括多电平单元的相变存储器件及其制造方法。 该装置包括从加热电极提供电流的第一相变材料层和与第一相变材料层连续形成且与第一相变材料层的宽度不同的第二相变材料层， 改变材料层，并且从加热电极提供电流。

公开(公告)号：US20090321705A1

公开(公告)日：2009-12-31

申请号：US12256385

申请日：2008-10-22

Applicant: Min Yong Lee ,  Su Jin Chae ,  Keum Bum Lee ,  Dong Ryeol Lee ,  Hyung Suk Lee

Inventor： Min Yong Lee ,  Su Jin Chae ,  Keum Bum Lee ,  Dong Ryeol Lee ,  Hyung Suk Lee

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.

Abstract translation: 相变存储器件包括半导体衬底，形成在半导体衬底上的第一导电图案，与第一导电图案的上表面接触并具有小于第一导电图案的直径的直径的第二导电图案，以及相位 改变与第二导电图案接触的材料层。

公开(公告)号：US20090045389A1

公开(公告)日：2009-02-19

申请号：US12169612

申请日：2008-07-08

Applicant: Yong Seok Eun ,  Su Jin Chae ,  Keum Bum Lee ,  Heon Yong Chang ,  Min Yong Lee

Inventor： Yong Seok Eun ,  Su Jin Chae ,  Keum Bum Lee ,  Heon Yong Chang ,  Min Yong Lee

IPC: H01L47/00 ,  H01L21/00

CPC classification number: H01L45/1233 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/16

Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.

Abstract translation: 相变存储装置及其制造方法。 该方法包括以下步骤：通过去除绝缘层的一部分来暴露底部电极，在其上依次形成底部电极和绝缘层的半导体衬底上限定底部电极接触孔; 在底部电极接触孔的内侧壁上形成非晶硅间隔物; 以及在底部电极接触孔中形成底部电极接触。

公开(公告)号：US07688570B2

公开(公告)日：2010-03-30

申请号：US12288880

申请日：2008-10-24

Applicant: Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

Inventor： Eun-A Lee ,  Ho-Jin Cho ,  Young-Dae Kim ,  Jun-Soo Chang ,  Su-Jin Chae ,  Hai-Won Kim

IPC: H01G4/06

CPC classification number: B82Y10/00 ,  H01G4/005 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract translation: 提供了一种具有纳米管的电容器及其制造方法。 所述电容器包括：下电极，其包括图案化导电层和形成在所述图案化导电层上的多个纳米管，所述多个纳米管不需要使用催化剂层; 形成在下电极上的电介质层; 以及形成在电介质层上的上电极。 该方法包括以下步骤：形成用于形成下电极的导电层; 在不使用催化剂层的情况下形成包括形成在所述导电层上的多个纳米管的纳米管阵列; 在纳米管阵列上形成介电层; 以及在所述电介质层上形成上电极。

公开(公告)号：US20090039334A1

公开(公告)日：2009-02-12

申请号：US12146184

申请日：2008-06-25

Applicant: Su Jin CHAE ,  Keum Bum LEE ,  Min Yong LEE

Inventor： Su Jin CHAE ,  Keum Bum LEE ,  Min Yong LEE

IPC: H01L45/00 ,  H01L21/311

CPC classification number: H01L45/06 ,  H01L27/2409

Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.

Abstract translation: 一种相变存储器件及其制造方法，其能够在使用PN二极管的相变存储器件中最小化用于形成PN二极管的接触孔的尺寸的同时降低驱动电流。 制造相变存储器件的方法包括以下步骤：制备具有与电介质层形成的结区的半导体衬底，在整个结构上形成具有低于电介质层的蚀刻选择性的层间电介质层，以及形成 通过去除层间电介质层和电介质层的预定部分的接触孔。 PN二极管和半导体衬底之间的接触面积增加，从而降低界面电阻。