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19 条记录 (耗时 0.018 秒)

    INTEGRATED CIRCUIT DEVICE HAVING GROUND OPEN DETECTION CIRCUIT
    13.
    发明申请
    INTEGRATED CIRCUIT DEVICE HAVING GROUND OPEN DETECTION CIRCUIT 有权
    具有接地开路检测电路的集成电路装置

    公开(公告)号：US20100271054A1

    公开(公告)日：2010-10-28

    申请号：US12764505

    申请日：2010-04-21

    申请人： Takayuki NAGASAWA

    发明人： Takayuki NAGASAWA

    IPC分类号： G01R27/08 ,  G01R31/14

    CPC分类号： G01R31/2853

    摘要： An integrated circuit device includes a chip having a power supply terminal, a ground terminal, an input terminal, and an internal circuit formed therein. The chip comprises: a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal.

    摘要翻译： 集成电路器件包括具有电源端子，接地端子，输入端子和形成在其中的内部电路的芯片。 该芯片包括：设置在输入端子和接地端子之间并从接地端子引导到输入端子的单向装置; 以及接地开路检测电路，包括：第一晶体管，其栅极连接到输入端子，源极和漏极连接在电源端子和接地端子之间;第二晶体管，其栅极连接到接地端子和源极; 连接在电源端子和接地端子之间的漏极以及用于分别在第一和第二晶体管的漏极与电源端子之间分别排列的节点的电位并用于输出接地开路检测信号的比较器。

    Integrated circuit with power state determination circuit
    14.
    发明授权
    Integrated circuit with power state determination circuit 有权
    具有电源状态确定电路的集成电路

    公开(公告)号：US08754632B2

    公开(公告)日：2014-06-17

    申请号：US13159543

    申请日：2011-06-14

    申请人： Hidetoshi Sugiyama ,  Takayuki Nagasawa ,  Hideaki Suzuki

    发明人： Hidetoshi Sugiyama ,  Takayuki Nagasawa ,  Hideaki Suzuki

    IPC分类号： G01R19/00

    CPC分类号： H01L27/0274 ,  G01R31/026 ,  G01R31/2884

    摘要： An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.

    摘要翻译： 形成有电源端子，接地端子，输入端子和内部电路的集成电路具有从输入端子到电源端子的方向的单向电路，单向电路设置在输入端子和 电源端子; 以及电源状态确定电路，其检测电源端子是否连接到外部电源以输出电源打开检测信号。 单向电路包括：第一晶体管，其中电源端子的电压施加到栅极;以及第二晶体管，其串联连接到第一晶体管，并且外部电源的电压被输入到输入端子。

    Resist composition and patterning process using the same
    15.
    发明授权
    Resist composition and patterning process using the same 有权
    抗蚀剂组成和图案化工艺使用相同

    公开(公告)号：US08748076B2

    公开(公告)日：2014-06-10

    申请号：US13345355

    申请日：2012-01-06

    申请人： Takayuki Nagasawa ,  Tomohiro Kobayashi ,  Ryosuke Taniguchi ,  Masaki Ohashi

    发明人： Takayuki Nagasawa ,  Tomohiro Kobayashi ,  Ryosuke Taniguchi ,  Masaki Ohashi

    IPC分类号： G03F7/039 ,  G03F7/20 ,  G03F7/30 ,  G03F7/38

    CPC分类号： G03F7/0045 ,  G03F7/0046 ,  G03F7/0397 ,  G03F7/2041

    摘要： There is disclosed a resist composition comprising at least: (A) a polymer containing one or more repeating units having a structure shown by the following general formula (1) and/or (2), an alkaline-solubility of the polymer being increased by an acid, (B) a photo acid generator generating, with responding to a high energy beam, a sulfonic acid shown by the following general formula (3), and (C) an onium sulfonate shown by the following general formula (4). There can be a resist composition showing not only excellent LWR and pattern profile but also extremely good performance in pattern-fall resistance, and to provide a patterning process using the same.

    摘要翻译： 公开了一种抗蚀剂组合物，其至少包含：（A）含有一个或多个具有下列通式（1）和/或（2）所示结构的重复单元的聚合物，该聚合物的碱溶性通过 一种酸，（B）一种光酸反应器，其响应于高能束，产生由以下通式（3）表示的磺酸，和（C）由以下通式（4）表示的磺酸盐。 可以存在不仅具有优异的LWR和图案轮廓的抗蚀剂组合物，而且还具有极好的抗倒伏性能，并且提供使用其的图案化工艺。

    Semiconductor memory device
    17.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06459641B2

    公开(公告)日：2002-10-01

    申请号：US09834945

    申请日：2001-04-16

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    IPC分类号： G11C700

    CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

    摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

    摘要翻译： 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

    Semiconductor memory device
    19.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6088291A

    公开(公告)日：2000-07-11

    申请号：US147600

    申请日：1999-01-29

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/005 ,  G11C2207/065

    摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

    摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。