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公开(公告)号：US08806386B2
公开(公告)日：2014-08-12
申请号：US12625749
申请日：2009-11-25
Applicant: Ying-Chou Cheng , Ru-Gun Liu , Josh J. H. Feng , Tsong-Hua Ou , Luke Lo , Chih-Ming Lai , Wen-Chun Huang
Inventor： Ying-Chou Cheng , Ru-Gun Liu , Josh J. H. Feng , Tsong-Hua Ou , Luke Lo , Chih-Ming Lai , Wen-Chun Huang
IPC: G06F17/50
CPC classification number: G06F17/5068
Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.
Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括提供电路的IC设计布局; 根据电路的电气参数和IC设计布局的光学参数对IC设计布局进行电气图案化（ePatterning）修改; 然后根据IC设计布局制造掩模。
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12.发明授权Method, system, and apparatus for adjusting local and global pattern density of an integrated circuit design 有权用于调整集成电路设计的局部和全局图案密度的方法，系统和装置公开(公告)号：US08372742B2
公开(公告)日：2013-02-12
申请号：US12712665
申请日：2010-02-25
Applicant: Ying-Chou Cheng , Cheng-Lung Stanley Tsai , Tsong-Hua Ou , Cheng Kun Tsai , Ru-Gun Liu , Wen-Chun Huang
Inventor： Ying-Chou Cheng , Cheng-Lung Stanley Tsai , Tsong-Hua Ou , Cheng Kun Tsai , Ru-Gun Liu , Wen-Chun Huang
IPC: H01L21/82
CPC classification number: G06F17/5068
Abstract: An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.
Abstract translation: 一种提供电路设计布局的集成电路（IC）设计方法，其具有彼此远离设置的多个功能块; 将电路设计布局上的近似虚拟区域的局部图案密度识别在与功能块之一预定义的距离内; 根据局部图案密度对近似虚拟区进行局部虚拟插入; 重复对所述功能块中的至少一些其他功能块的识别和执行; 并且根据全局模式密度对非局部虚拟区域实施全局虚拟插入。
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13.发明授权公开(公告)号：US08219951B2
公开(公告)日：2012-07-10
申请号：US12713902
申请日：2010-02-26
Applicant: Ying-Chou Cheng , Tsong-Hua Ou , Chih-Wei Hsu , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang , Boren Luo
Inventor： Ying-Chou Cheng , Tsong-Hua Ou , Chih-Wei Hsu , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang , Boren Luo
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.
Abstract translation: 本公开提供了一种集成电路方法。 该方法包括提供集成电路（IC）设计布局; 模拟IC设计布局的热效应; 基于模拟热效应模拟IC设计布局的电气性能; 并基于模拟电气性能对IC设计布局进行热虚拟插入。
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公开(公告)号：US08201111B2
公开(公告)日：2012-06-12
申请号：US13195907
申请日：2011-08-02
Applicant: Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
Inventor： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F17/5081
Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
Abstract translation: 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。
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公开(公告)号：US20070232402A1
公开(公告)日：2007-10-04
申请号：US11397272
申请日：2006-04-03
Applicant: Ying-Chou Cheng
Inventor： Ying-Chou Cheng
IPC: F16D7/02
CPC classification number: F16D7/024
Abstract: A clutch includes a hub having a hub flange formed at a first end. The clutch further includes a clutch tube having a central aperture formed therein, a clutch tube flange, and a friction surface that is substantially planar. The central aperture is configured to receive the shaft and is substantially perpendicular to the friction surface. The clutch further includes a clutch plate having a clutch surface that is substantially planar and is in contact with the friction surface. The clutch further includes a fastener configured to couple the clutch plate to the hub; and a spring device configured to push the hub flange and the clutch tube flange away from one another and push the friction surface to contact the clutch surface.
Abstract translation: 离合器包括具有在第一端形成的轮毂凸缘的轮毂。 离合器还包括其中形成有中心孔的离合器管，离合器管凸缘和基本上平面的摩擦表面。 中心孔被构造成接收轴并基本上垂直于摩擦表面。 离合器还包括离合器片，该离合器片具有基本平坦且与摩擦表面接触的离合器表面。 离合器还包括被配置成将离合器片联接到轮毂的紧固件; 以及弹簧装置，其构造成将轮毂凸缘和离合器管凸缘彼此远离推动并推动摩擦表面接触离合器表面。
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Patent Agency Ranking
公开(公告)号：US08745554B2
公开(公告)日：2014-06-03
申请号：US12647997
申请日：2009-12-28
Applicant: Ying-Chou Cheng , Tsong-Hua Ou , Josh J. H. Feng , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang
Inventor： Ying-Chou Cheng , Tsong-Hua Ou , Josh J. H. Feng , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F2217/12 , Y02P90/265
Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.
Abstract translation: 本公开提供了许多不同实施例中的集成电路设计方法。 一种示例性的IC设计方法包括在第一技术节点中提供电路的IC设计布局; 将电路的IC设计布局迁移到第二个技术节点; 根据电路的电气参数对迁移的IC设计布局进行电气图案化（ePatterning）修改; 然后根据第二技术节点中的电路的迁移的IC设计布局制造掩模。
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公开(公告)号：US08673520B2
公开(公告)日：2014-03-18
申请号：US13046265
申请日：2011-03-11
Applicant: George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
Inventor： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC: G03F1/00
CPC classification number: G06F17/5068 , G03F1/00 , G03F1/68
Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
Abstract translation: 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。 第一和第二阵列的每个特征包括设置在衰减材料区域中的开口。
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公开(公告)号：US20120040278A1
公开(公告)日：2012-02-16
申请号：US13281198
申请日：2011-10-25
Applicant: George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
Inventor： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC: G03F1/38
CPC classification number: G06F17/5068 , G03F1/00 , G03F1/68
Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
Abstract translation: 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。
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公开(公告)号：US20110217630A1
公开(公告)日：2011-09-08
申请号：US13046265
申请日：2011-03-11
Applicant: George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
Inventor： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC: G03F1/00
CPC classification number: G06F17/5068 , G03F1/00 , G03F1/68
Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
Abstract translation: 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。 第一和第二阵列的每个特征包括设置在衰减材料区域中的开口。
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20.发明申请公开(公告)号：US20110214101A1
公开(公告)日：2011-09-01
申请号：US12713902
申请日：2010-02-26
Applicant: Ying-Chou Cheng , Tsong-Hua Ou , Chih-Wei Hsu , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang , Boren Luo
Inventor： Ying-Chou Cheng , Tsong-Hua Ou , Chih-Wei Hsu , Cheng-Lung Tsai , Ru-Gun Liu , Wen-Chun Huang , Boren Luo
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.
Abstract translation: 本公开提供了一种集成电路方法。 该方法包括提供集成电路（IC）设计布局; 模拟IC设计布局的热效应; 基于模拟热效应模拟IC设计布局的电气性能; 并基于模拟电气性能对IC设计布局进行热虚拟插入。
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