公开(公告)号：US07867924B2

公开(公告)日：2011-01-11

申请号：US12038278

申请日：2008-02-27

Applicant: Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

Inventor： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

IPC: H01L21/4763

CPC classification number: H01L21/76224 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

Abstract translation: 制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。 在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。 上沟槽形成在上半导体衬底内。 上部器件隔离膜形成在上部沟槽内。 用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

公开(公告)号：US07842569B2

公开(公告)日：2010-11-30

申请号：US11618155

申请日：2006-12-29

Applicant: Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

Inventor： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

IPC: H01L21/00

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract translation: 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。

公开(公告)号：US20100167490A1

公开(公告)日：2010-07-01

申请号：US12629920

申请日：2009-12-03

Applicant: Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

Inventor： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC: H01L21/762

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

Abstract translation: 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US08367535B2

公开(公告)日：2013-02-05

申请号：US13053668

申请日：2011-03-22

Applicant: Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

Inventor： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

IPC: H01L21/28

CPC classification number: H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

Abstract: Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

Abstract translation: 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

公开(公告)号：US20110281427A1

公开(公告)日：2011-11-17

申请号：US13053668

申请日：2011-03-22

Applicant: Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

Inventor： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

IPC: H01L21/28

CPC classification number: H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

Abstract: Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

Abstract translation: 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

公开(公告)号：US20110207334A1

公开(公告)日：2011-08-25

申请号：US12902212

申请日：2010-10-12

Applicant: Yong-soon CHOI ,  Hong-gun KIM ,  Ha-young YI ,  Gil-heyun CHOI ,  Eun-kee Hong

Inventor： Yong-soon CHOI ,  Hong-gun KIM ,  Ha-young YI ,  Gil-heyun CHOI ,  Eun-kee Hong

IPC: H01L21/31

CPC classification number: H01L21/02126 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76224

Abstract: A method of manufacturing a semiconductor device includes an improved technique of filling a trench to provide the resulting semiconductor device with better characteristics and higher reliability. The method includes forming a trench in a semiconductor layer, forming a first layer on the semiconductor layer using a silicon source and a nitrogen source to fill the trench, curing the first layer using an oxygen source, and annealing the second layer. The method may also be used to form other types of insulating layers such as an interlayer insulating layer.

Abstract translation: 一种制造半导体器件的方法包括一种填充沟槽的改进技术，以使得到的半导体器件具有更好的特性和更高的可靠性。 该方法包括在半导体层中形成沟槽，使用硅源和氮源在半导体层上形成第一层以填充沟槽，使用氧源固化第一层，并退火第二层。 该方法也可用于形成其它类型的绝缘层，例如层间绝缘层。

公开(公告)号：US20080035984A1

公开(公告)日：2008-02-14

申请号：US11618155

申请日：2006-12-29

Applicant: Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

Inventor： Hong-Gun KIM ,  Ju-Seon GOO ,  Mun-Jun KIM ,  Yong-Soon CHOI ,  Sung-Tae KIM ,  Eun-Kyung BAEK

IPC: H01L29/788 ,  H01L21/762

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

Abstract translation: 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。