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    Method of fabricating semiconductor device
    1.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08367535B2

    公开(公告)日：2013-02-05

    申请号：US13053668

    申请日：2011-03-22

    申请人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

    发明人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

    摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

    摘要翻译： 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20110281427A1

    公开(公告)日：2011-11-17

    申请号：US13053668

    申请日：2011-03-22

    申请人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

    发明人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

    摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

    摘要翻译： 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

    Semiconductor device isolation structures and methods of fabricating such structures
    7.
    发明授权
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US07674685B2

    公开(公告)日：2010-03-09

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。

    Flash memory device and method of fabricating the same
    8.
    发明授权
    Flash memory device and method of fabricating the same 有权
    闪存装置及其制造方法

    公开(公告)号：US07842569B2

    公开(公告)日：2010-11-30

    申请号：US11618155

    申请日：2006-12-29

    申请人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Hong-Gun Kim ,  Ju-Seon Goo ,  Mun-Jun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： One embodiment of a method of fabricating a flash memory device includes forming a trench mask pattern, which includes a gate insulation pattern and a charge storage pattern stacked in sequence, on a semiconductor substrate; etching the semiconductor substrate using the trench mask pattern as an etch mask to form trenches defining active regions; and sequentially forming lower and upper device isolation patterns in the trench. After sequentially forming an intergate insulation film and a control gate film on the upper device isolation pattern, the control gate film, the intergate insulation pattern and the gloating gate pattern are formed, thereby providing gate lines crossing over the active regions.

    摘要翻译： 制造闪速存储器件的方法的一个实施例包括在半导体衬底上形成沟槽掩模图案，其包括依次层叠的栅极绝缘图案和电荷存储图案; 使用沟槽掩模图案作为蚀刻掩模蚀刻半导体衬底，以形成限定有源区的沟槽; 并且顺序地形成沟槽中的下部和上部器件隔离图案。 在上部器件隔离图案上顺序地形成栅极间绝缘膜和控制栅极膜之后，形成控制栅极膜，栅极间绝缘图案和阴极管栅极图案，从而提供跨越有源区域的栅极线。

    Semiconductor device isolation structures and methods of fabricating such structures
    10.
    发明申请
    Semiconductor device isolation structures and methods of fabricating such structures 有权
    半导体器件隔离结构及其制造方法

    公开(公告)号：US20080014711A1

    公开(公告)日：2008-01-17

    申请号：US11654588

    申请日：2007-01-18

    申请人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    发明人： Jong-Wan Choi ,  Ju-Seon Goo ,  Hong-Gun Kim ,  Yong-Soon Choi ,  Sung-Tae Kim ,  Eun-Kyung Baek

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/11531

    摘要： Disclosed are methods for fabricating semiconductor devices incorporating a composite trench isolation structure comprising a first oxide pattern, a SOG pattern and a second oxide pattern wherein the oxide patterns enclose the SOG pattern. The methods include the deposition of a first oxide layer and a SOG layer to fill recessed trench regions formed in the substrate. The first oxide layer and the SOG layer are then subjected to a planarization sequence including a CMP process followed by an etchback process to form a composite structure having a substantially flat upper surface that exposes both the oxide and the SOG material. The second oxide layer is then applied and subjected to a similar CMP/etchback sequence to obtain a composite structure having an upper surface that is recessed relative to a plane defined by the surfaces of adjacent active regions.

    摘要翻译： 公开了用于制造半导体器件的方法，该半导体器件结合有包括第一氧化物图案，SOG图案和第二氧化物图案的复合沟槽隔离结构，其中氧化物图案包围SOG图案。 所述方法包括沉积第一氧化物层和SOG层以填充形成在衬底中的凹陷沟槽区域。 然后对第一氧化物层和SOG层进行包括CMP工艺的随后的回蚀工艺的平坦化顺序，以形成具有露出氧化物和SOG材料的基本上平坦的上表面的复合结构。 然后施加第二氧化物层并进行类似的CMP /回蚀序列以获得具有相对于由相邻有源区的表面限定的平面凹进的上表面的复合结构。