公开(公告)号：US20080206954A1

公开(公告)日：2008-08-28

申请号：US12038278

申请日：2008-02-27

申请人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

发明人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

摘要翻译： 制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。 在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。 上沟槽形成在上半导体衬底内。 上部器件隔离膜形成在上部沟槽内。 用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

公开(公告)号：US07867924B2

公开(公告)日：2011-01-11

申请号：US12038278

申请日：2008-02-27

申请人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

发明人： Jong-wan Choi ,  Eun-kyung Baek ,  Sang-hoon Ahn ,  Hong-gun Kim ,  Dong-chul Suh ,  Yong-soon Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： A method of fabricating a semiconductor device includes forming a lower device on a lower semiconductor substrate, and forming an interlayer insulating film on the lower device. An upper semiconductor substrate is formed on the interlayer insulating film such that the interlayer insulating film is between the lower and upper semiconductor substrates. Upper trenches are formed within the upper semiconductor substrate. An upper device isolating film is formed within the upper trenches. The upper device isolating film is irradiated with ultraviolet light having a wavelength configured to break chemical bonds of impurities in the upper device isolating film to reduce an impurity concentration thereof.

摘要翻译： 制造半导体器件的方法包括在下半导体衬底上形成下部器件，并在下部器件上形成层间绝缘膜。 在层间绝缘膜上形成上半导体衬底，使得层间绝缘膜位于下半导体衬底和上半导体衬底之间。 上沟槽形成在上半导体衬底内。 上部器件隔离膜形成在上部沟槽内。 用上述器件隔离膜中的杂质化学键的波长的紫外线照射上部器件隔离膜以降低其杂质浓度。

公开(公告)号：US08455985B2

公开(公告)日：2013-06-04

申请号：US13019520

申请日：2011-02-02

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

IPC分类号： H01L29/00

CPC分类号： H01L23/562 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L23/5258 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

摘要翻译： 集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件 在复合层间绝缘层中。 第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容 绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。

公开(公告)号：US20120094437A1

公开(公告)日：2012-04-19

申请号：US13235717

申请日：2011-09-19

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Baek ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Baek ,  Kyoung-hee Kim ,  Byung-lyul Park ,  Byung-hee Kim

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

摘要翻译： 通过硅通孔（TSV）形成的方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k介电材料，通过蚀刻主通孔中的低k电介质形成次级通孔 以同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

公开(公告)号：US08426308B2

公开(公告)日：2013-04-23

申请号：US13235717

申请日：2011-09-19

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-Iyul Park ,  Byung-hee Kim

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-Iyul Park ,  Byung-hee Kim

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

摘要翻译： 通过硅通孔（TSV）形成的方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k介电材料，通过蚀刻主通孔中的低k电介质形成次级通孔 以同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。

公开(公告)号：US20110241184A1

公开(公告)日：2011-10-06

申请号：US13019520

申请日：2011-02-02

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Eunkee Hong

IPC分类号： H01L29/00

CPC分类号： H01L23/562 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/76801 ,  H01L21/76825 ,  H01L23/5258 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.

摘要翻译： 集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件 在复合层间绝缘层中。 第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容 绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。