公开(公告)号：US07705644B2

公开(公告)日：2010-04-27

申请号：US12028936

申请日：2008-02-11

申请人： Ho-young Kim ,  Dong-bee Jang ,  Jae-yoon Sim ,  Young-sang Kim

发明人： Ho-young Kim ,  Dong-bee Jang ,  Jae-yoon Sim ,  Young-sang Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

摘要翻译： 宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。 与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且 由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。 控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。

公开(公告)号：US20080191765A1

公开(公告)日：2008-08-14

申请号：US12028936

申请日：2008-02-11

申请人： Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

发明人： Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

IPC分类号： H03L7/00 ,  G11C5/14 ,  G05F3/16

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

摘要翻译： 宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。 与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且 由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。 控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。

公开(公告)号：US20060044217A1

公开(公告)日：2006-03-02

申请号：US11199991

申请日：2005-08-10

申请人： Young-sang Kim ,  Kun-tae Kim

发明人： Young-sang Kim ,  Kun-tae Kim

IPC分类号： G09G5/00

CPC分类号： H04N5/4401 ,  G06F3/1423 ,  H04N5/44591 ,  H04N5/46 ,  H04N21/4122 ,  H04N21/42638 ,  H04N21/43632 ,  H04N21/43637 ,  H04N21/4622 ,  H04N21/485 ,  H04N21/6131

摘要： An image providing system and a method thereof, wherein the image providing system includes a host device for receiving video signals from video input sources and for processing the received video signals, a wireless display device, connected wirelessly to the host device, for displaying an image corresponding to a first of the processed video signals if the first video signal is received, and a wire-based display device, connected by wire to the host device, for displaying an image corresponding to a second of the processed video signals that is different from the first video signal if the second video signal is received. Accordingly, many users can view different images using a plurality of display devices of one image providing system.

摘要翻译： 一种图像提供系统及其方法，其中所述图像提供系统包括用于从视频输入源接收视频信号并处理所接收的视频信号的主机设备，无线连接到所述主机设备的无线显示设备，用于显示图像 如果接收到第一视频信号，则对应于处理的视频信号中的第一视频信号，以及通过有线连接到主机设备的线性显示设备，用于显示对应于处理的视频信号中的第二处理视频信号的图像 第一视频信号如果接收到第二视频信号。 因此，许多用户可以使用一个图像提供系统的多个显示设备来查看不同的图像。

公开(公告)号：US06098161A

公开(公告)日：2000-08-01

申请号：US105247

申请日：1998-06-26

申请人： Young-Sang Kim

发明人： Young-Sang Kim

IPC分类号： H04L27/00 ,  H04B3/10 ,  H04B7/005 ,  H04J11/00 ,  H04L5/06 ,  H04L25/03 ,  H04L27/01 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03159 ,  H04L2025/03414 ,  H04L2025/03522

摘要： A method and an apparatus for generating address of a coefficient memory in an OFDM adaptive channel equalizer are disclosed. The address generating apparatus comprises a signal generator for generating a symbol identification signal according to modulo-(Y+1) operation on symbol numbers within one OFDM transmission frame; a first pulse generator for generating a first pulse signal synchronized with a sample clock according to the location of the pilot signal within each symbol respective to the symbol identification signal; a write address generator for generating a write address of the coefficient memory by the first pulse signal and the symbol identification signal; a second pulse generator for generating a second pulse signal by frequency-dividing the sample clock by Y; and a read address generator for generating a read address of the coefficient memory by the second pulse signal. Therefore, the address and the enable signal for the coefficient memory can be simply generated by using the sequential circuit such as the counter, thereby accessing efficiently the updated coefficient value according to the pilot insertion principle.

摘要翻译： 公开了一种用于在OFDM自适应信道均衡器中产生系数存储器的地址的方法和装置。 地址发生装置包括信号发生器，用于根据在一个OFDM传输帧内的码元号进行模（Y + 1）操作产生码元识别信号; 第一脉冲发生器，用于根据与符号识别信号相对应的每个符号内的导频信号的位置，产生与采样时钟同步的第一脉冲信号; 写地址发生器，用于通过第一脉冲信号和符号识别信号产生系数存储器的写入地址; 第二脉冲发生器，用于通过将采样时钟分频Y来产生第二脉冲信号; 以及读地址发生器，用于通过第二脉冲信号产生系数存储器的读地址。 因此，可以通过使用诸如计数器的顺序电路简单地生成用于系数存储器的地址和使能信号，从而根据导频插入原理有效地访问更新的系数值。

公开(公告)号：US5963592A

公开(公告)日：1999-10-05

申请号：US982222

申请日：1997-12-01

申请人： Young-Sang Kim

发明人： Young-Sang Kim

IPC分类号： H04J11/00 ,  H04B7/005 ,  H04L25/03 ,  H04L27/26 ,  H04N7/015 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03038 ,  H04L5/0048 ,  H04L2025/03414 ,  H04L5/0007

摘要： An adaptive channel equalizer for use in OFDM receiver is disclosed. The adaptive channel equalizer comprises a first complex multiplier for outputting a first in-phase complex multiplication signal and a first quadrature phase complex multiplication signal; a reference signal generator for generating a reference signal; an error calculator for outputting an in-phase error signal and a quadrature phase error signal; a delay unit for outputting an in-phase delay signal and a quadrature phase delay signal; a gain controller for outputting an in-phase gain control signal and a quadrature phase gain control signal; a second complex multiplier for outputting a second in-phase complex multiplication signal and a second quadrature phase complex multiplication signal; an adder for outputting updated in-phase and quadrature phase coefficients; an address generator for generating a write address signal and a read address signal; a storage unit for storing the updated in-phase and quadrature phase coefficients, and outputting the updated coefficients; an initial coefficients generator for generating an initial coefficients; a selecting signal generator for generating a selecting signal; and a multiplexing unit for selecting one of the initial coefficients and the updated coefficients according to the selecting signal.

摘要翻译： 公开了一种用于OFDM接收机的自适应信道均衡器。 自适应信道均衡器包括用于输出第一同相复数乘法信号和第一正交相位复数乘法信号的第一复数乘法器; 用于产生参考信号的参考信号发生器; 用于输出同相误差信号和正交相位误差信号的误差计算器; 用于输出同相延迟信号和正交相位延迟信号的延迟单元; 用于输出同相增益控制信号和正交相位增益控制信号的增益控制器; 用于输出第二同相复数乘法信号和第二正交相位复数乘法信号的第二复数乘法器; 用于输出更新的同相和正交相位系数的加法器; 用于产生写入地址信号和读取地址信号的地址发生器; 存储单元，用于存储更新的同相和正交相位系数，并输出更新的系数; 用于产生初始系数的初始系数发生器; 选择信号发生器，用于产生选择信号; 以及复用单元，用于根据选择信号选择初始系数和更新的系数之一。

公开(公告)号：US5502507A

公开(公告)日：1996-03-26

申请号：US373153

申请日：1995-01-17

申请人： Young-Sang Kim

发明人： Young-Sang Kim

IPC分类号： H04B7/005 ,  H04L25/03 ,  H04N5/00 ,  H04N5/21 ,  H04N7/015 ,  H04N7/12

CPC分类号： H04L25/0305 ,  H04N5/211

摘要： An improved equalization apparatus includes a coefficient update module for receiving a filtered signal from the equalizer filter circuit and for generating a set of filter coefficients including a set of coarsely updated coefficients or a set of finely updated coefficients for equalizer filter. The coefficient updating module includes a first memory means for storing a set of coarse error values, and for generating, in response to a filtered data sample, a first error signal representative of the corresponding coarse error value; and a second memory for storing a set of fine error values, and for generating, in response to a filtered data sample and a control signal, a second error signal representative of the corresponding fine error value.

摘要翻译： 改进的均衡装置包括系数更新模块，用于从均衡器滤波器电路接收滤波后的信号，并产生一组滤波器系数，包括一组粗略更新的系数或一组用于均衡滤波器的精细更新的系数。 所述系数更新模块包括用于存储一组粗略误差值的第一存储器装置，并且用于响应于滤波数据采样产生表示对应的粗略误差值的第一误差信号; 以及第二存储器，用于存储一组精细误差值，并且响应于滤波数据采样和控制信号，产生表示对应的精细误差值的第二误差信号。

公开(公告)号：US5491518A

公开(公告)日：1996-02-13

申请号：US375326

申请日：1995-01-18

申请人： Young-Sang Kim

发明人： Young-Sang Kim

IPC分类号： H04B7/005 ,  H04L25/03 ,  H04N5/00 ,  H04N5/21 ,  H04N7/015

CPC分类号： H04N5/211 ,  H04L25/0305

摘要： An improved equalization apparatus includes updating circuit for generating, in response to the received television signal and the error signal, a set of updated filter coefficients as the set of the filter coefficients for the equalizer filter, which comprises: a shift register for storing and shifting a data sample to provide a set of the data samples; a multiplier for multiplying a error signal with the set of the data samples to provide a set of error weighted data samples; a scaling circuit, in response to a blind mode signal, for scaling down the set of error weighted data samples with a first scale value in order to generate a first set of scaled error weighted data samples and, in response to a decision mode signal, for scaling down the set of error weighted data samples with a second scale value to generate a second set of scaled error weighted data samples; an adder for adding the first or the second set of scaled error weighted data samples to a set of previous filter coefficients in order to produce a set of updated filter coefficients as an output of the updating circuit; and a FIFO buffer for storing the set of updated filter coefficients as the set of previous filter coefficients for the adder.

摘要翻译： 改进的均衡装置包括更新电路，用于响应于所接收的电视信号和误差信号，生成一组更新的滤波器系数作为用于均衡器滤波器的滤波器系数的集合，其包括：用于存储和移位的移位寄存器 提供一组数据样本的数据样本; 用于将误差信号与所述数据样本集合相乘以提供一组误差加权数据样本的乘法器; 缩放电路，响应于盲模式信号，用于以第一刻度值缩小所述误差加权数据样本集合，以便生成第一组缩放误差加权数据样本，并且响应于判定模式信号， 用于以第二比例值缩小所述误差加权数据样本集合，以生成第二组缩放误差加权数据样本; 加法器，用于将第一或第二组缩放的误差加权数据样本相加到一组先前的滤波器系数，以便产生一组更新的滤波器系数作为更新电路的输出; 以及用于将更新的滤波器系数集合存储为用于加法器的先前滤波器系数的集合的FIFO缓冲器。

公开(公告)号：US09209517B2

公开(公告)日：2015-12-08

申请号：US13983568

申请日：2012-02-08

申请人： Sang-Hoon Choi ,  Young-Sang Kim ,  Bu-Seok Shim

发明人： Sang-Hoon Choi ,  Young-Sang Kim ,  Bu-Seok Shim

IPC分类号： H01Q1/24 ,  H01Q1/52 ,  H01Q9/04 ,  H01Q21/28

CPC分类号： H01Q1/523 ,  H01Q1/241 ,  H01Q1/521 ,  H01Q9/0421 ,  H01Q21/28

摘要： A MIMO/diversity antenna for improving isolation of a frequency band includes: a ground surface formed on a printed circuit board; planar inverted F antennas having the ground surface therebetween and disposed on the printed circuit board having no ground surface formed, each F antenna having an antenna pattern that includes a radiation unit, a power supply unit, and a ground unit; power supply pads and ground pads formed on the printed circuit board having no ground surface formed corresponding to the power supply unit and the ground unit of the antenna pattern in the planar inverted F antennas; and connection patterns connecting the ground surface with each ground pad to electrically connect the ground surface to each ground unit of the antenna pattern in the planar inverted F antennas. At least one of the connection patterns is formed with a strip line of a meandering shape.

摘要翻译： 用于改善频带隔离的MIMO /分集天线包括：形成在印刷电路板上的接地面; 每个F天线具有包括辐射单元，电源单元和接地单元的天线方向图，所述F天线具有接地表面，并且布置在没有形成地面的印刷电路板上; 形成在印刷电路板上的电源焊盘和接地焊盘，其没有对应于平面倒F形天线中的电源单元和天线图案的接地单元形成的接地表面; 以及将地面与每个接地焊盘连接的连接图案，以将平面倒置的F天线中的地面与天线方向图的每个接地单元电连接。 连接图案中的至少一个形成有蜿蜒形状的带状线。

公开(公告)号：US20130307744A1

公开(公告)日：2013-11-21

申请号：US13983568

申请日：2012-02-08

申请人： Sang-Hoon Choi ,  Young-Sang Kim ,  Bu-Seok Shim

发明人： Sang-Hoon Choi ,  Young-Sang Kim ,  Bu-Seok Shim

IPC分类号： H01Q1/52

CPC分类号： H01Q1/523 ,  H01Q1/241 ,  H01Q1/521 ,  H01Q9/0421 ,  H01Q21/28

摘要： A MIMO/diversity antenna for improving isolation of a frequency band includes: a ground surface formed on a printed circuit board; planar inverted F antennas having the ground surface therebetween and disposed on the printed circuit board having no ground surface formed, each F antenna having an antenna pattern that includes a radiation unit, a power supply unit, and a ground unit; power supply pads and ground pads formed on the printed circuit board having no ground surface formed corresponding to the power supply unit and the ground unit of the antenna pattern in the planar inverted F antennas; and connection patterns connecting the ground surface with each ground pad to electrically connect the ground surface to each ground unit of the antenna pattern in the planar inverted F antennas. At least one of the connection patterns is formed with a strip line of a meandering shape.

摘要翻译： 用于改善频带隔离的MIMO /分集天线包括：形成在印刷电路板上的接地面; 每个F天线具有包括辐射单元，电源单元和接地单元的天线方向图，所述F天线具有接地表面，并且布置在没有形成地面的印刷电路板上; 形成在印刷电路板上的电源焊盘和接地焊盘，其没有对应于平面倒F形天线中的电源单元和天线图案的接地单元形成的接地表面; 以及将地面与每个接地焊盘连接的连接图案，以将平面倒置的F天线中的地面与天线方向图的每个接地单元电连接。 连接图案中的至少一个形成有蜿蜒形状的带状线。

公开(公告)号：US20130234288A1

公开(公告)日：2013-09-12

申请号：US13614893

申请日：2012-09-13

申请人： Sung Mo GU ,  Moon Hyung CHO ,  Young Sang KIM ,  Jong Bum PARK

发明人： Sung Mo GU ,  Moon Hyung CHO ,  Young Sang KIM ,  Jong Bum PARK

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L28/60

摘要： A method for manufacturing a MIM capacitor trench structure includes forming a lower metal film on an inter-metal dielectric; forming a first inter-metal dielectric on the lower metal film; forming a first trench; sequentially forming a dielectric film and a first barrier metal film along the bottom surface and sidewalls of the first trench; and filling the first trench with a conductive material to form a first upper metal film. Further, the method includes forming a second inter-metal dielectric on the first upper metal film; forming a second trench; forming a via hole in a via hole region of the second inter-metal dielectric; forming a second barrier metal film along the bottom surface and sidewalls of the second trench; and filling the via hole and the second trench with the conductive material to form a via contact and a second upper metal film.

摘要翻译： 一种用于制造MIM电容器沟槽结构的方法，包括在金属间电介质上形成下金属膜; 在下金属膜上形成第一金属间电介质; 形成第一沟槽; 沿着第一沟槽的底表面和侧壁依次形成电介质膜和第一阻挡金属膜; 以及用导电材料填充所述第一沟槽以形成第一上金属膜。 此外，该方法包括在第一上金属膜上形成第二金属间电介质; 形成第二沟槽; 在所述第二金属间电介质的通孔区域中形成通孔; 沿着第二沟槽的底表面和侧壁形成第二阻挡金属膜; 以及用所述导电材料填充所述通孔和所述第二沟槽，以形成通孔接触和第二上部金属膜。