公开(公告)号：US07101769B2

公开(公告)日：2006-09-05

申请号：US10776546

申请日：2004-02-10

Applicant: Seung-Beom Kim ,  Won-Mo Park ,  Yun-Jae Lee ,  Joon-Mo Kwon ,  Myoung-Hee Han ,  Man-Jong Yu

Inventor： Seung-Beom Kim ,  Won-Mo Park ,  Yun-Jae Lee ,  Joon-Mo Kwon ,  Myoung-Hee Han ,  Man-Jong Yu

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.

Abstract translation: 本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积，同时防止在下电极之间形成电桥。 该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。 将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。 然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。 清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

公开(公告)号：USD794037S1

公开(公告)日：2017-08-08

申请号：US29518341

申请日：2015-02-23

Applicant: Yun Jae Lee ,  Goonies Co., Ltd.

Designer： Yun Jae Lee

公开(公告)号：US20150048464A1

公开(公告)日：2015-02-19

申请号：US14254871

申请日：2014-04-16

Applicant: JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

Inventor： JEONG-HEON PARK ,  KI-WOONG KIM ,  HEE-JU SHIN ,  JOON-MYOUNG LEE ,  WOO-JIN KIM ,  JAE-HOON KIM ,  SE-CHUNG OH ,  YUN-JAE LEE

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3272 ,  H01L23/528 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract translation: 提供了具有彼此间隔开的自由层和钉扎层的半导体器件。 在自由层和钉扎层之间形成隧道势垒层。 被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。 可以在下钉扎层和上钉扎层之间形成间隔件。 非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。

公开(公告)号：US20110094587A1

公开(公告)日：2011-04-28

申请号：US12707392

申请日：2010-02-17

Applicant: Kyung Youl BAEK ,  Hoichang Yang ,  Seung Sang Hwang ,  Yeon Hee Choi ,  Yun-Jae Lee ,  Dong Yeop Oh ,  Han Sup Lee

Inventor： Kyung Youl BAEK ,  Hoichang Yang ,  Seung Sang Hwang ,  Yeon Hee Choi ,  Yun-Jae Lee ,  Dong Yeop Oh ,  Han Sup Lee

IPC: H01L31/0256 ,  H01L51/40 ,  H01L51/30

CPC classification number: H01L51/0043 ,  G03F7/0002 ,  H01L51/0036 ,  H01L51/0541 ,  H01L51/0545 ,  Y02E10/549

Abstract: Provided is a method for controlling a self-assembled structure of a poly(3-hexylthiophene)-based block copolymer, including: providing a polymer composition containing a block copolymer having a π-conjugated poly(3-hexylthiophene) polymer and a non-conjugated polymer introduced thereto, and a solvent; and coating the polymer composition onto a substrate.According to the method disclosed herein, it is possible to control a self-assembled structure of a poly(3-hexylthiophene)-based block copolymer merely by a relatively simple process including coating the poly(3-hexylthiophene)-based block copolymer onto a substrate with a selected solvent. In this manner, it is possible to control the alignment of conductive domains in the block copolymer so that it is suitable for various organic electronic devices. In addition, the self-assembled polymer structure having various self-assembled structures controlled selectively by the method may be applied to organic electronic devices for designing and developing high-quality devices.

Abstract translation: 提供一种用于控制聚（3-己基噻吩）基嵌段共聚物的自组装结构的方法，包括：提供含有具有共轭聚（3-己基噻吩）聚合物的嵌段共聚物和非共轭 引入其中的共轭聚合物和溶剂; 并将聚合物组合物涂覆到基底上。 根据本文公开的方法，仅通过相对简单的方法可以控制聚（3-己基噻吩）基嵌段共聚物的自组装结构，包括将聚（3-己基噻吩）基嵌段共聚物涂覆在 底物与选定的溶剂。 以这种方式，可以控制嵌段共聚物中的导电畴的取向，使其适用于各种有机电子器件。 此外，通过该方法选择性地控制的具有各种自组装结构的自组装聚合物结构可以应用于用于设计和开发高质量器件的有机电子器件。

公开(公告)号：US08968984B2

公开(公告)日：2015-03-03

申请号：US13574354

申请日：2010-11-19

Applicant: Pil Rye Yang ,  Kyung Keun Yoon ,  Yun Jae Lee

Inventor： Pil Rye Yang ,  Kyung Keun Yoon ,  Yun Jae Lee

IPC: G03F7/00 ,  G03F7/028

CPC classification number: G03F7/028 ,  G03F7/0007 ,  G03F7/038 ,  G03F7/0758

Abstract: Disclosed is a photosensitive resin composition for an organic insulating layer. More specifically, the photosensitive resin composition is suitable for forming a substrate of a transflective thin film transistor liquid crystal display (TFT-LCD) or a pattern of an interlayer insulating layer by improving remarkably a pattern property with a high taper angle besides improvement of flatness, sensitivity, heat resistance, and transparency. Particularly, the photosensitive resin composition can provide low power dissipation besides a wide viewing angle and high visibility when being applied to a transflective type display. In addition, the photosensitive resin composition can provide a clear screen under natural light without a backlight by maintaining the brightness of a screen and prominent field visibility.

Abstract translation: 公开了一种有机绝缘层用感光性树脂组合物。 更具体地，感光性树脂组合物适合于通过除了改善平坦度以外，通过显着提高具有高锥角的图案特性来形成透反射薄膜晶体管液晶显示器（TFT-LCD）的基板或层间绝缘层的图案 ，灵敏度，耐热性和透明度。 特别是，当应用于半透反射型显示器时，感光性树脂组合物除了具有广视角和高可见度外，还能够提供低功耗。 此外，感光性树脂组合物可以通过保持屏幕的亮度和突出的视场可视性而在自然光下提供无背光的清晰屏幕。

公开(公告)号：US20140021426A1

公开(公告)日：2014-01-23

申请号：US13927090

申请日：2013-06-25

Applicant: Yun-jae LEE ,  Woo-jin KIM ,  Joon-myoung LEE

Inventor： Yun-jae LEE ,  Woo-jin KIM ,  Joon-myoung LEE

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic device comprises a memory cell comprising a magnetic resistance device and lower and upper electrodes with the magnetic resistance device interposed therebetween to apply current to the magnetic resistance device. The magnetic resistance device includes: a buffer layer for controlling a crystalline axis for inducing perpendicular magnetic anisotropy (PMA) in the magnetic resistance device, the buffer layer being in contact with the lower electrode; a seed layer being in contact with the buffer layer and being oriented to a hexagonal close-packed lattice (HCP) (0001) crystal plane; and a perpendicularly magnetized pinned layer being in contact with the seed layer and having an L11 type ordered structure.

Abstract translation: 一种磁性装置包括一个包含一个磁阻装置的存储单元和一个介于它们之间的磁阻装置的下电极和上电极，以向磁阻装置施加电流。 磁阻元件包括：缓冲层，用于控制在磁阻器件中引起垂直磁各向异性（PMA）的晶轴，缓冲层与下电极接触; 种子层与缓冲层接触并取向为六方密堆积晶格（HCP）（0001）晶面; 并且垂直磁化的钉扎层与种子层接触并且具有L11型有序结构。

公开(公告)号：US20120139021A1

公开(公告)日：2012-06-07

申请号：US13241435

申请日：2011-09-23

Applicant: Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

Inventor： Seok-Hyun Kim ,  Deok-Sung Hwang ,  Yun-Jae Lee ,  Chul Lee ,  Yoon-Taek Jang ,  Chang-Hoon Jeon ,  Sang-Bin Ahn ,  Jun-Hyeok Ahn

IPC: H01L27/108

CPC classification number: H01L27/10876 ,  H01L21/765

Abstract: A semiconductor memory device includes a transistor having a channel region buried in a substrate and source/drain regions formed to provide low contact resistance. A field isolation structure is formed in the substrate to define active structures. The field isolation structure includes a gap-fill pattern, a first material layer surrounding the gap-fill pattern, and a second material layer surrounding at least a portion of the first material layer. Each active structure includes a first active pattern having a top surface located beneath the level of the top surface of the field isolation structure, and a second active pattern disposed on the first active pattern and whose top is located above the level of the top surface of the field isolation structure.

Abstract translation: 半导体存储器件包括具有掩埋在衬底中的沟道区和形成为提供低接触电阻的源极/漏极区的晶体管。 在衬底中形成场隔离结构以限定有源结构。 场隔离结构包括间隙填充图案，围绕间隙填充图案的第一材料层和围绕第一材料层的至少一部分的第二材料层。 每个有源结构包括第一有源图案，其具有位于场隔离结构的顶表面的平面下方的顶表面，以及布置在第一有源图案上的第二有源图案，其顶部位于第一有源图案的顶表面的高度之上 现场隔离结构。

公开(公告)号：US20060255391A1

公开(公告)日：2006-11-16

申请号：US11459595

申请日：2006-07-24

Applicant: Seung-Beom KIM ,  Won-Mo PARK ,  Yun-Jae LEE ,  Joon-Mo KWON ,  Myoung-Hee HAN ,  Man-Jong YU

Inventor： Seung-Beom KIM ,  Won-Mo PARK ,  Yun-Jae LEE ,  Joon-Mo KWON ,  Myoung-Hee HAN ,  Man-Jong YU

IPC: H01L29/00 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.

Abstract translation: 本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积同时防止在下电极之间形成电桥。 该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。 将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。 然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。 清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

公开(公告)号：US06221778B1

公开(公告)日：2001-04-24

申请号：US09368166

申请日：1999-08-05

Applicant: Yun-Jae Lee

Inventor： Yun-Jae Lee

IPC: H01L21311

CPC classification number: H01L29/6659 ,  H01L21/31116 ,  H01L21/76834

Abstract: A method of fabricating semiconductor device, which reduces amount of oxidization on semiconductor substrate to suppress volume expansion of an active region of a semiconductor substrate, thereby removing pits on the semiconductor substrate. A conductive layer for forming a gate electrode and a first insulating layer serving as a mask are sequentially formed on the semiconductor substrate. Using a mask for forming a gate electrode, the first insulating layer and the conductive layer are sequentially etched to form a gate electrode. A second insulating layer and a third insulating layer are formed on the structure of the gate electrode and the surface of the semiconductor substrate. A third insulating layer formed on an overall surface of the semiconductor substrate is dry etched to form an insulating layer spacer on sidewalls of the gate electrode. A fourth insulating layer is formed on the structure of the semiconductor substrate and the gate electrode by a deposition process. That is, after forming an insulating layer spacer on sidewalls of the gate electrode, an oxide layer is formed by a deposition process so as to compensate for damage.

Abstract translation: 一种制造半导体器件的方法，其减少半导体衬底上的氧化量，以抑制半导体衬底的有源区的体积膨胀，从而去除半导体衬底上的凹坑。 用于形成栅电极的导电层和用作掩模的第一绝缘层依次形成在半导体衬底上。 使用用于形成栅电极的掩模，依次蚀刻第一绝缘层和导电层以形成栅电极。 在栅电极的结构和半导体衬底的表面上形成第二绝缘层和第三绝缘层。 形成在半导体基板的整个表面上的第三绝缘层被干蚀刻以在栅电极的侧壁上形成绝缘层间隔物。 通过沉积工艺在半导体衬底和栅电极的结构上形成第四绝缘层。 也就是说，在栅电极的侧壁上形成绝缘层间隔物之后，通过沉积工艺形成氧化物层以补偿损伤。